bag3_digital.layout.stdcells.gates

This module contains layout generators for various logic gates.

Module Contents

Classes

InvCore	A single inverter.
InvChainCore	An inverter chain.
InvTristateCore	A gated inverter with two enable signals.
NAND2Core	A 2-input NAND gate.
NANDNOR3Core	A 3-input NAND/NOR gate.
NAND3Core	A 3-input NAND gate.
NOR3Core	A 3-input NOR gate.
NOR2Core	A 2-input NOR gate.
PassGateCore	CMOS pass gate

Functions

get_adj_tidx_list(→ Tuple[bag.util.math.HalfInt, ...)	Helper method that gives two adjacent signal wires, with sig_locs override.
get_adj_tid_list(...)

class bag3_digital.layout.stdcells.gates.InvCore(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: xbase.layout.mos.base.MOSBase

A single inverter.

classmethod get_schematic_class() → Optional[Type[bag.design.module.Module]]

classmethod get_params_info() → Dict[str, str]

Returns a dictionary from parameter names to descriptions.

Returns:

param_info – dictionary from parameter names to descriptions.

Return type:

Mapping[str, str]

classmethod get_default_param_values() → Dict[str, Any]

Returns a dictionary containing default parameter values.

Override this method to define default parameter values. As good practice, you should avoid defining default values for technology-dependent parameters (such as channel length, transistor width, etc.), but only define default values for technology-independent parameters (such as number of tracks).

Returns:

default_params – dictionary of default parameter values.

Return type:

Mapping[str, Any]

draw_layout() → None

Draw the layout of this template.

Override this method to create the layout.

WARNING: you should never call this method yourself.

class bag3_digital.layout.stdcells.gates.InvChainCore(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: xbase.layout.mos.base.MOSBase

An inverter chain.

Assumes:

1. PMOS row above NMOS row.

2. PMOS gate connections on bottom, NMOS gate connections on top.

property out_invert: bool

property num_stages: int

classmethod get_schematic_class() → Optional[Type[bag.design.module.Module]]

classmethod get_params_info() → Dict[str, str]

Returns a dictionary from parameter names to descriptions.

Returns:

param_info – dictionary from parameter names to descriptions.

Return type:

Mapping[str, str]

classmethod get_default_param_values() → Dict[str, Any]

Returns a dictionary containing default parameter values.

Override this method to define default parameter values. As good practice, you should avoid defining default values for technology-dependent parameters (such as channel length, transistor width, etc.), but only define default values for technology-independent parameters (such as number of tracks).

Returns:

default_params – dictionary of default parameter values.

Return type:

Mapping[str, Any]

draw_layout() → None

Draw the layout of this template.

Override this method to create the layout.

WARNING: you should never call this method yourself.

_create_masters(pinfo: xbase.layout.mos.base.MOSBasePlaceInfo) → Sequence[InvCore]

_update_inst_sig_locs(sig_locs: Mapping[str, Union[float, bag.util.math.HalfInt]], sig_map_list: Sequence[Tuple[str, str]], layer: int, inst: bag.layout.template.PyLayInstance) → None

class bag3_digital.layout.stdcells.gates.InvTristateCore(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: xbase.layout.mos.base.MOSBase

A gated inverter with two enable signals.

classmethod get_schematic_class() → Optional[Type[bag.design.module.Module]]

classmethod get_params_info() → Dict[str, str]

Returns a dictionary from parameter names to descriptions.

Returns:

param_info – dictionary from parameter names to descriptions.

Return type:

Mapping[str, str]

classmethod get_default_param_values() → Dict[str, Any]

Returns a dictionary containing default parameter values.

Override this method to define default parameter values. As good practice, you should avoid defining default values for technology-dependent parameters (such as channel length, transistor width, etc.), but only define default values for technology-independent parameters (such as number of tracks).

Returns:

default_params – dictionary of default parameter values.

Return type:

Mapping[str, Any]

draw_layout() → None

Draw the layout of this template.

Override this method to create the layout.

WARNING: you should never call this method yourself.

class bag3_digital.layout.stdcells.gates.NAND2Core(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: xbase.layout.mos.base.MOSBase

A 2-input NAND gate.

‘out’ and ‘in’ pin direction is determined by vertical_out and vertical_in flags, respectively but regardless, in0_vm, in1_vm, out_vm, and out_hm are always available, and also if connect_inputs is True in0_hm, in1_hm will also be available.

Assumes:

1. PMOS row above NMOS row.

2. PMOS gate connections on bottom, NMOS gate connections on top.

classmethod get_schematic_class() → Optional[Type[bag.design.module.Module]]

classmethod get_params_info() → Dict[str, str]

Returns a dictionary from parameter names to descriptions.

Returns:

param_info – dictionary from parameter names to descriptions.

Return type:

Mapping[str, str]

classmethod get_default_param_values() → Dict[str, Any]

Returns a dictionary containing default parameter values.

Override this method to define default parameter values. As good practice, you should avoid defining default values for technology-dependent parameters (such as channel length, transistor width, etc.), but only define default values for technology-independent parameters (such as number of tracks).

Returns:

default_params – dictionary of default parameter values.

Return type:

Mapping[str, Any]

draw_layout() → None

Draw the layout of this template.

Override this method to create the layout.

WARNING: you should never call this method yourself.

class bag3_digital.layout.stdcells.gates.NANDNOR3Core(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: xbase.layout.mos.base.MOSBase

A 3-input NAND/NOR gate.

‘out’ and ‘in’ pin direction is determined by vertical_out and vertical_in flags, respectively but regardless, in0_vm, in1_vm, in2_vm, out_vm, and out_hm are always available

Assumes:

1. PMOS row above NMOS row.

2. PMOS gate connections on bottom, NMOS gate connections on top.

classmethod get_params_info() → Dict[str, str]

Returns a dictionary from parameter names to descriptions.

Returns:

param_info – dictionary from parameter names to descriptions.

Return type:

Mapping[str, str]

classmethod get_default_param_values() → Dict[str, Any]

Returns a dictionary containing default parameter values.

Override this method to define default parameter values. As good practice, you should avoid defining default values for technology-dependent parameters (such as channel length, transistor width, etc.), but only define default values for technology-independent parameters (such as number of tracks).

Returns:

default_params – dictionary of default parameter values.

Return type:

Mapping[str, Any]

draw_layout() → None

Draw the layout of this template.

Override this method to create the layout.

WARNING: you should never call this method yourself.

draw_series_network(w: int, seg: int, stack: int, ridx: int, **kwargs: Any) → Tuple[Tuple[List[List[bag.layout.routing.base.WireArray]], List[bag.layout.routing.base.WireArray], List[bag.layout.routing.base.WireArray]], int]

draw_parallel_network(w: int, seg: int, stack: int, ridx: int, **kwargs: Any) → Tuple[Tuple[List[List[bag.layout.routing.base.WireArray]], List[bag.layout.routing.base.WireArray], List[bag.layout.routing.base.WireArray]], int]

draw_series_network_stack_even(w: int, seg: int, stack: int, ridx: int) → Tuple[Tuple[List[List[bag.layout.routing.base.WireArray]], List[bag.layout.routing.base.WireArray], List[bag.layout.routing.base.WireArray]], int]

draw_parallel_network_stack_even(w: int, seg: int, stack: int, ridx: int) → Tuple[Tuple[List[List[bag.layout.routing.base.WireArray]], List[bag.layout.routing.base.WireArray], List[bag.layout.routing.base.WireArray]], int]

draw_series_network_stack_odd(w: int, seg: int, stack: int, ridx: int, is_nmos: bool, sig_locs: Mapping[str, Union[float, bag.util.math.HalfInt]], ref_width: int = 0) → Tuple[Tuple[List[List[bag.layout.routing.base.WireArray]], List[bag.layout.routing.base.WireArray], List[bag.layout.routing.base.WireArray]], int]

draw_parallel_network_stack_odd(w: int, seg: int, stack: int, ridx: int, split: bool = True, ref_width: int = 0) → Tuple[Tuple[List[List[bag.layout.routing.base.WireArray]], List[bag.layout.routing.base.WireArray], List[bag.layout.routing.base.WireArray]], int]

draw_network_shared_stack_odd(w: int, seg: int, stack: int, ridx: int, ref_width: int = 0) → Tuple[xbase.layout.mos.data.MOSPorts, xbase.layout.mos.data.MOSPorts, xbase.layout.mos.data.MOSPorts, int]

_get_gate_in_stack_even(idx: int, stack: int) → int

Left to right 0, 1, 2, …, nports-1, nports-1, nports-2, …, 0, 0, 1, … each element is repeated by number of stacks

_get_g_idx_list_stack_even(g_warr: bag.layout.routing.base.WireArray, seg: int, stack: int) → List[List[bag.layout.routing.base.WireArray]]

_get_closest_unused_tidx(sig_locs: Mapping[str, Union[float, bag.util.math.HalfInt]], layer: int, tidx_init: bag.util.math.HalfInt, tidx_min: bag.util.math.HalfInt = None, tidx_max: bag.util.math.HalfInt = None) → bag.util.math.HalfInt

static _check_tidx_unavailable(tidx: bag.util.math.HalfInt, sig_locs: Mapping[str, Union[float, bag.util.math.HalfInt]]) → bool

_get_hm_tid_list(ridx: int, sig_locs: Mapping[str, Union[float, bag.util.math.HalfInt]], key_name: str, stack: int, hm_layer: int, tr_w_h: int, up: bool) → List[bag.layout.routing.base.TrackID]

class bag3_digital.layout.stdcells.gates.NAND3Core(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: NANDNOR3Core

A 3-input NAND gate. Due to the similarities between NAND and NOR, please look at NANDNOR3Core for most of the implementation.

classmethod get_schematic_class() → Optional[Type[bag.design.module.Module]]

class bag3_digital.layout.stdcells.gates.NOR3Core(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: NANDNOR3Core

A 3-input NOR gate. Due to the similarities between NAND and NOR, please look at NANDNOR3Core for most of the implementation.

classmethod get_schematic_class() → Optional[Type[bag.design.module.Module]]

class bag3_digital.layout.stdcells.gates.NOR2Core(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: xbase.layout.mos.base.MOSBase

A 2-input NOR gate.

‘out’ and ‘in’ pin direction is determined by vertical_out and vertical_in flags, respectively but regardless, in0_vm, in1_vm, out_vm, and out_hm are always available, and also if connect_inputs is True in0_hm, in1_hm will also be available.

Assumes:

1. PMOS row above NMOS row.

2. PMOS gate connections on bottom, NMOS gate connections on top.

classmethod get_schematic_class() → Optional[Type[bag.design.module.Module]]

classmethod get_params_info() → Dict[str, str]

Returns a dictionary from parameter names to descriptions.

Returns:

param_info – dictionary from parameter names to descriptions.

Return type:

Mapping[str, str]

classmethod get_default_param_values() → Dict[str, Any]

Returns a dictionary containing default parameter values.

Override this method to define default parameter values. As good practice, you should avoid defining default values for technology-dependent parameters (such as channel length, transistor width, etc.), but only define default values for technology-independent parameters (such as number of tracks).

Returns:

default_params – dictionary of default parameter values.

Return type:

Mapping[str, Any]

draw_layout() → None

Draw the layout of this template.

Override this method to create the layout.

WARNING: you should never call this method yourself.

class bag3_digital.layout.stdcells.gates.PassGateCore(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: xbase.layout.mos.base.MOSBase

CMOS pass gate

classmethod get_schematic_class() → Optional[Type[bag.design.module.Module]]

classmethod get_params_info() → Dict[str, str]

Returns a dictionary from parameter names to descriptions.

Returns:

param_info – dictionary from parameter names to descriptions.

Return type:

Mapping[str, str]

classmethod get_default_param_values() → Dict[str, Any]

Returns a dictionary containing default parameter values.

Override this method to define default parameter values. As good practice, you should avoid defining default values for technology-dependent parameters (such as channel length, transistor width, etc.), but only define default values for technology-independent parameters (such as number of tracks).

Returns:

default_params – dictionary of default parameter values.

Return type:

Mapping[str, Any]

draw_layout() → None

Draw the layout of this template.

Override this method to create the layout.

WARNING: you should never call this method yourself.

bag3_digital.layout.stdcells.gates.get_adj_tidx_list(layout: xbase.layout.mos.base.MOSBase, ridx: int, sig_locs: Mapping[str, Union[float, bag.util.math.HalfInt]], wtype: xbase.layout.enum.MOSWireType, prefix: str, up: bool) → Tuple[bag.util.math.HalfInt, bag.util.math.HalfInt]

Helper method that gives two adjacent signal wires, with sig_locs override.

bag3_digital.layout.stdcells.gates.get_adj_tid_list(layout: xbase.layout.mos.base.MOSBase, ridx: int, sig_locs: Mapping[str, Union[float, bag.util.math.HalfInt]], wtype: xbase.layout.enum.MOSWireType, prefix: str, up: bool, tr_w_h: int) → Tuple[bag.layout.routing.base.TrackID, bag.layout.routing.base.TrackID]