xbase.layout.mos.base

Module Contents

Classes

SupplyColumnInfo

MOSBase

The base template class.

Functions

_row_check(→ int)

class xbase.layout.mos.base.SupplyColumnInfo[source]
ncol: int[source]
top_layer: int[source]
tr_info: List[Tuple[int, bag.util.math.HalfInt]][source]
class xbase.layout.mos.base.MOSBase(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)[source]

Bases: bag.layout.template.TemplateBase, abc.ABC

The base template class.

Parameters:

  • temp_db (TemplateDB) – the template database.

  • params (Param) – the parameter values.

  • log_file (str) – the log file path.

  • log_level (LogLevel) – the logging level.

  • **kwargs (Any) –

    dictionary of the following optional parameters:

    gridRoutingGrid

    the routing grid to use for this template.

property used_array: xbase.layout.mos.util.MOSUsedArray[source]

the transistor usage map object.

Type:

MOSUsedArray

property num_cols: int[source]

number of transistors.

Type:

int

property num_rows: int[source]

Total number of transistor rows.

Type:

int

property num_tile_rows: int[source]

Number of tiles

Type:

int

property tile_size: Tuple[int, int][source]

Tuple of (num_cols, num_tiles).

Type:

Tuple[int, int]

property place_info: xbase.layout.mos.placement.data.MOSBasePlaceInfo[source]

The tile 0 layout information object.

Type:

MOSBasePlaceInfo

property draw_base_info: Tuple[xbase.layout.mos.placement.data.TilePatternElement, xbase.layout.mos.placement.data.TileInfoTable][source]
property flipped: bool[source]

True if tile 0 is flipped.

Type:

bool

property arr_info: xbase.layout.mos.placement.data.MOSArrayPlaceInfo[source]
property tile_table: xbase.layout.mos.placement.data.TileInfoTable[source]
property tech_cls: xbase.layout.mos.tech.MOSTech[source]

the primitive technology information object.

Type:

MOSTech

property top_layer: int[source]

the ID of transistor port layer.

Type:

int

property conn_layer: int[source]

the ID of transistor port layer.

Type:

int

property tr_manager: bag.layout.routing.base.TrackManager[source]

the track manager object.

Type:

TrackManager

property sd_pitch: int[source]

the source-drain pitch.

Type:

int

property min_sep_col: int[source]

column separation needed between transistors.

Type:

int

property sub_sep_col: int[source]

column separation needed between transistor/substrate and substrate/substrate.

This is guaranteed to be even.

Type:

int

property gr_sub_sep_col: int[source]

column separation needed between guard ring substrate and inner substrate.

Type:

int

property min_sub_col: int[source]

Minimum number of fingers for substrate contact.

Type:

int

property can_short_adj_tracks: bool[source]

True if you can short adjacent transistor ports using hm_layer.

Type:

bool

property can_draw_double_gate: bool[source]

True if double gates are supported.

Type:

bool

property has_double_guard_ring: bool[source]

True if the PDK requires double guard ring.

Type:

bool

can_abut_mos(row_info: xbase.layout.mos.data.MOSRowInfo) → bool[source]

bool: True if you can abut mos by sharing drain or source.

can_extend_ds_conn(g_side: bool, threshold: str) → bool[source]
Parameters:

  • g_side (bool) – True for checking for extension on gate side, False for checking on the other side

  • threshold (str) – Threshold of mos in the row

Returns:

ans – True if you extend drain or source on conn_layer, on the gate side or the other side.

Return type:

bool

draw_base(obj: Union[xbase.layout.mos.placement.data.MOSBasePlaceInfo, xbase.layout.mos.placement.data.TilePatternElement, Tuple[Union[xbase.layout.mos.placement.data.MOSBasePlaceInfo, xbase.layout.mos.placement.data.TilePattern, xbase.layout.mos.placement.data.TilePatternElement], xbase.layout.mos.placement.data.TileInfoTable]], flip_tile: bool = False, mirror: bool = True) → None[source]
get_tile_pattern_element(mult: int = 1, mirror: bool = True, flip: bool = False) → xbase.layout.mos.placement.data.TilePatternElement[source]
get_tile_subpattern(start_idx: int, stop_idx: int, mult: int = 1, mirror: bool = True, flip: bool = False) → xbase.layout.mos.placement.data.TilePatternElement[source]
get_draw_base_sub_pattern(start_idx: int, stop_idx: int, mirror: bool = True, flip: bool = False) → Tuple[xbase.layout.mos.placement.data.TilePatternElement, xbase.layout.mos.placement.data.TileInfoTable][source]
get_hm_sp_le_sep_col(ntr: int = 1) → int[source]

Get number of columns needed to satisfy hm_layer line-end spacing.

This is a convenient wrapper around RoutingGrid.get_line_end_sep_tracks(). See documentation for that method for more details.

get_tile_info(tile_idx: int) → Tuple[xbase.layout.mos.placement.data.MOSBasePlaceInfo, int, bool][source]
get_tile_pinfo(tile_idx: int) → xbase.layout.mos.placement.data.MOSBasePlaceInfo[source]
get_num_wires(row_idx: int, wire_type: Union[xbase.layout.enum.MOSWireType, bool], wire_name: str, *, tile_idx: int = 0) → int[source]
get_track_info(row_idx: int, wire_type: Union[xbase.layout.enum.MOSWireType, bool], wire_name: str, wire_idx: int = 0, *, tile_idx: int = 0) → Tuple[bag.util.math.HalfInt, int][source]
get_track_index(row_idx: int, wire_type: Union[xbase.layout.enum.MOSWireType, bool], wire_name: str, wire_idx: int = 0, *, tile_idx: int = 0) → bag.util.math.HalfInt[source]
get_track_id(row_idx: int, wire_type: Union[xbase.layout.enum.MOSWireType, bool], wire_name: str, wire_idx: int = 0, *, tile_idx: int = 0) → bag.layout.routing.base.TrackID[source]

Get the TrackID of the specified hm_layer routing track.

Parameters:

  • row_idx (int) – the transistor row index.

  • wire_type (Union[MOSWireType, bool]) –

    wire type used to determined where to look for the specified wire. In an unflipped row, gate type means search in the bottom wire group, and drain/source type means search in the top wire group.

    If a bool is given, then True means the top wires, False, means the bottom wires.

  • wire_name (str) – the wire name.

  • wire_idx (int) – the wire index.

  • tile_idx (int) – the tile index.

Returns:

track_id – the TrackID representing the specified hm_layer routing track.

Return type:

TrackID

get_hm_track_info(hm_layer: int, wire_name: str, wire_idx: int = 0, *, tile_idx: int = 0) → Tuple[bag.util.math.HalfInt, int][source]
get_hm_track_id(hm_layer: int, wire_name: str, wire_idx: int = 0, *, tile_idx: int = 0) → bag.layout.routing.base.TrackID[source]
get_hm_track_index(hm_layer: int, wire_name: str, wire_idx: int = 0, *, tile_idx: int = 0) → bag.util.math.HalfInt[source]
get_row_info(row_idx: int, tile_idx: int = 0) → xbase.layout.mos.data.MOSRowInfo[source]
set_mos_size(num_cols: int = 0, num_tiles: int = 0) → None[source]
add_tile(master: MOSBase, tile_idx: int, col_idx: int, *, flip_lr: bool = False, commit: bool = True) → bag.layout.core.PyLayInstance[source]
add_mos(row_idx: int, col_idx: int, seg: int, *, tile_idx: int = 0, w: int = 0, g_on_s: bool = False, stack: int = 1, flip_lr: bool = False, **kwargs: Any) → xbase.layout.mos.data.MOSPorts[source]
add_nand2(row_idx: int, col_idx: int, seg: int, *, tile_idx: int = 0, w: int = 0, stack: int = 1, flip_lr: bool = False, export_mid: bool = False, other: bool = False) → xbase.layout.mos.data.NAND2Ports[source]
get_supply_column_info(top_layer: int, tile_idx: int = 0) → SupplyColumnInfo[source]
add_supply_column(sup_info: SupplyColumnInfo, col_idx: int, vdd_table: Dict[int, List[bag.layout.routing.base.WireArray]], vss_table: Dict[int, List[bag.layout.routing.base.WireArray]], ridx_p: int = -1, ridx_n: int = 0, tile_idx: int = 0, flip_lr: bool = False, extend_vdd: bool = True, extend_vss: bool = True, min_len_mode: pybag.enum.MinLenMode = MinLenMode.NONE, **kwargs: Any) → None[source]
add_tap(col_idx: int, vdd_list: List[bag.layout.routing.base.WireArray], vss_list: List[bag.layout.routing.base.WireArray], *, seg: int = 0, tile_idx: int = 0, flip_lr: bool = False, **kwargs: Any) → int[source]

Add substrate contacts in all transistor rows in the given tile.

This method will automatically add substrate contact in all transistor rows at the given column, and avoid checker-board implant DRC error for you.

NOTE: substrate contacts won’t be drawn in substrate only rows.

Parameters:

  • col_idx (int) – the anchor column index.

  • vdd_list (List[WireArray]) – all supply conn_layer ports will be appended to this list.

  • vss_list (List[WireArray]) – all ground conn_layer ports will be appended to this list.

  • seg (int) – number of substrate contact segments.

  • tile_idx (int) – tile index.

  • flip_lr (bool) – True to flip left-and-right.

  • **kwargs (Any) – keyword arguments for add_substrate_contact() method.

Returns:

tap_ncol – number of columns used

Return type:

int

get_tap_ncol(seg: int = 0, tile_idx: int = 0) → int[source]
add_substrate_contact(row_idx: int, col_idx: int, *, tile_idx: int = 0, seg: int = 0, flip_lr: bool = False, port_mode: xbase.layout.enum.SubPortMode = SubPortMode.EVEN, **kwargs: Any) → bag.layout.routing.base.WireArray[source]
_tile_check(tile_idx: int) → int[source]
_handle_abutment(abut_list: List[xbase.layout.mos.data.MOSAbutInfo]) → None[source]
classmethod get_mos_row_info(pinfo: xbase.layout.mos.placement.data.MOSBasePlaceInfo, tile_yb: int, flip_tile: bool, row_idx: int) → Tuple[xbase.layout.mos.data.MOSRowInfo, int, pybag.enum.Orientation][source]
classmethod register_device(used_arr: xbase.layout.mos.util.MOSUsedArray, tile_idx: int, row_idx: int, col_idx: int, seg: int, flip_lr: bool, linfo: xbase.layout.mos.data.MOSEdgeInfo, rinfo: xbase.layout.mos.data.MOSEdgeInfo, tinfo: xbase.layout.mos.data.BlkExtInfo, binfo: xbase.layout.mos.data.BlkExtInfo, abut_list: Optional[List[xbase.layout.mos.data.MOSAbutInfo]]) → Tuple[int, pybag.enum.Orientation][source]
xbase.layout.mos.base._row_check(pinfo: xbase.layout.mos.placement.data.MOSBasePlaceInfo, row_idx: int) → int[source]