`bag.design.module`

design_model(key: Any) → None[source]

set_param(key: str, val: Union[int, float, bool, str]) → None[source]

Set schematic parameters for this master.

This method is only used to set parameters for BAG primitives.

Parameters:

key (str) – parameter name.
val (Union[int, float, bool, str]) – parameter value.

finalize() → None[source]: Finalize this master instance.

get_content(output_type: pybag.enum.DesignOutput, rename_dict: Dict[str, str], name_prefix: str, name_suffix: str, shell: bool, exact_cell_names: Set[str], supply_wrap_mode: pybag.enum.SupplyWrapMode) → Tuple[str, Any][source]

Returns the content of this master instance.

Parameters:

output_type (DesignOutput) – the output type.
rename_dict (Dict[str, str]) – the renaming dictionary.
name_prefix (str) – the name prefix.
name_suffix (str) – the name suffix.
shell (bool) – True if we’re just producing a shell content (i.e. just top level block).
exact_cell_names (Set[str]) – set of cell names to keep exact (don’t add prefix and suffix)
supply_wrap_mode (SupplyWrapMode) – the netlisting supply wrap mode.

Returns:

cell_name (str) – the master cell name.
content (Any) – the master content data structure.

get_model_path(output_type: pybag.enum.DesignOutput, view_name: str = '') → pathlib.Path[source]: Returns the model file path.

should_delete_instance() → bool[source]

Returns True if this instance should be deleted based on its parameters.

This method is mainly used to delete 0 finger or 0 width transistors. However, You can override this method if there exists parameter settings which corresponds to an empty schematic.

Returns:: delete – True if parent should delete this instance.
Return type:: bool

get_schematic_parameters() → Mapping[str, str][source]

Returns the schematic parameter dictionary of this instance.

NOTE: This method is only used by BAG primitives, as they are implemented with parameterized cells in the CAD database. Custom subclasses should not override this method.

Returns:: params – the schematic parameter dictionary.
Return type:: Mapping[str, str]

get_cell_name_from_parameters() → str[source]

Returns new cell name based on parameters.

NOTE: This method is only used by BAG primitives. This method enables a BAG primitive to change the cell master based on design parameters (e.g. change transistor instance based on the intent parameter). Custom subclasses should not override this method.

Returns:: cell – the cell name based on parameters.
Return type:: str

rename_pin(old_pin: str, new_pin: str) → None[source]

Renames an input/output pin of this schematic.

NOTE: Make sure to call reconnect_instance_terminal() so that instances are connected to the new pin.

Parameters:

old_pin (str) – the old pin name.
new_pin (str) – the new pin name.

add_pin(new_pin: str, pin_type: Union[pybag.enum.TermType, str], sig_type: pybag.enum.SigType = SigType.signal) → None[source]

Adds a new pin to this schematic.

NOTE: Make sure to call reconnect_instance_terminal() so that instances are connected to the new pin.

Parameters:

new_pin (str) – the new pin name.
pin_type (Union[TermType, str]) – the new pin type.
sig_type (SigType) – the signal type of the pin.

get_signal_type(pin_name: str) → pybag.enum.SigType[source]

remove_pin(remove_pin: str) → bool[source]

Removes a pin from this schematic.

Parameters:: remove_pin (str) – the pin to remove.
Returns:: success – True if the pin is successfully found and removed.
Return type:: bool

set_pin_attribute(pin_name: str, key: str, val: str) → None[source]

Set an attribute on the given pin.

Parameters:

pin_name (str) – the pin name.
key (str) – the attribute name.
val (str) – the attribute value.

rename_instance(old_name: str, new_name: str, conn_list: Optional[Union[Iterable[Tuple[str, str]], ItemsView[str, str]]] = None) → None[source]

Renames an instance in this schematic.

Parameters:

old_name (str) – the old instance name.
new_name (str) – the new instance name.
conn_list (Optional[Union[Iterable[Tuple[str, str]], ItemsView[str, str]]]) – an optional connection list.

remove_instance(inst_name: str) → bool[source]

Removes the instance with the given name.

Parameters:: inst_name (str) – the child instance to delete.
Returns:: success – True if the instance is successfully found and removed.
Return type:: bool

delete_instance(inst_name: str) → bool[source]

Delete the instance with the given name.

This method is identical to remove_instance(). It’s here only for backwards compatibility.

replace_instance_master(inst_name: str, lib_name: str, cell_name: str, static: bool = False, keep_connections: bool = False) → None[source]

Replace the master of the given instance.

NOTE: all terminal connections will be reset. Call reconnect_instance_terminal() to modify terminal connections.

Parameters:

inst_name (str) – the child instance to replace.
lib_name (str) – the new library name.
cell_name (str) – the new cell name.
static (bool) – True if we’re replacing instance with a static schematic instead of a design module.
keep_connections (bool) – True to keep the old connections when the instance master changed.

reconnect_instance_terminal(inst_name: str, term_name: str, net_name: str) → None[source]

Reconnect the instance terminal to a new net.

Parameters:

inst_name (str) – the instance to modify.
term_name (str) – the instance terminal name to reconnect.
net_name (str) – the net to connect the instance terminal to.

reconnect_instance(inst_name: str, term_net_iter: Union[Iterable[Tuple[str, str]], ItemsView[str, str]]) → None[source]

Reconnect all give instance terminals

Parameters:

inst_name (str) – the instance to modify.
term_net_iter (Union[Iterable[Tuple[str, str]], ItemsView[str, str]]) – an iterable of (term, net) tuples.

array_instance(inst_name: str, inst_name_list: Optional[List[str]] = None, term_list: Optional[List[Dict[str, str]]] = None, inst_term_list: Optional[List[Tuple[str, Iterable[Tuple[str, str]]]]] = None, dx: int = 0, dy: int = 0) → None[source]

Replace the given instance by an array of instances.

This method will replace self.instances[inst_name] by a list of Modules. The user can then design each of those modules.

Parameters:

inst_name (str) – the instance to array.
inst_name_list (Optional[List[str]]) – a list of the names for each array item.
term_list (Optional[List[Dict[str, str]]]) – a list of modified terminal connections for each array item. The keys are instance terminal names, and the values are the net names to connect them to. Only terminal connections different than the parent instance should be listed here. If None, assume terminal connections are not changed.
inst_term_list (Optional[List[Tuple[str, List[Tuple[str, str]]]]]) – zipped version of inst_name_list and term_list. If given, this is used instead.
dx (int) – the X coordinate shift. If dx = dy = 0, default to shift right.
dy (int) – the Y coordinate shift. If dx = dy = 0, default to shift right.

design_sources_and_loads(params_list: Optional[Sequence[Mapping[str, Any]]] = None, default_name: str = 'VDC') → None[source]

Convenience function for generating sources and loads,

Given DC voltage/current bias sources information, array the given voltage/current bias sources and configure the voltage/current.

Each bias dictionary is a dictionary from bias source name to a 3-element list. The first two elements are the PLUS/MINUS net names, respectively, and the third element is the DC voltage/current value as a string or float. A variable name can be given to define a testbench parameter.

Parameters:

params_list (Optional[Sequence[Mapping[str, Any]]]) –
List of dictionaries representing the element to be used Each dictionary should have the following format:

’lib’: Optional[str] (default: analogLib) -> lib name of the master ‘type’: str -> type of of the master (i.e ‘vdc’) ‘value’: Union[T, Dict[str, T], T = Union[str, float, int] -> value of the master ‘conns’: Dict[str, str] -> connections of the master
default_name (str) – Default name of the instance in the testbench

design_dummy_transistors(dum_info: List[Tuple[Any]], inst_name: str, vdd_name: str, vss_name: str, net_map: Optional[Dict[str, str]] = None) → None[source]

Convenience function for generating dummy transistor schematic.

Given dummy information (computed by AnalogBase) and a BAG transistor instance, this method generates dummy schematics by arraying and modifying the BAG transistor instance.

Parameters:

dum_info (List[Tuple[Any]]) – the dummy information data structure.
inst_name (str) – the BAG transistor instance name.
vdd_name (str) – VDD net name. Used for PMOS dummies.
vss_name (str) – VSS net name. Used for NMOS dummies.
net_map (Optional[Dict[str, str]]) – optional net name transformation mapping.

design_transistor(inst_name: str, w: int, lch: int, seg: int, intent: str, m: str = '', d: str = '', g: Union[str, List[str]] = '', s: str = '', b: str = '', stack: int = 1, mos_type: str = '') → None[source]

Design a BAG_prim transistor (with stacking support).

This is a convenient method to design a stack transistor. Additional transistors will be created on the right. The intermediate nodes of each parallel segment are not shorted together.

Parameters:

inst_name (str) – name of the BAG_prim transistor instance.
w (int) – the width of the transistor, in number of fins or resolution units.
lch (int) – the channel length, in resolution units.
seg (int) – number of parallel segments of stacked transistors.
intent (str) – the threshold flavor.
m (str) – base name of the intermediate nodes. the intermediate nodes will be named ‘midX’, where X is a non-negative integer.
d (str) – the drain name. Empty string to not rename.
g (Union[str, List[str]]) – the gate name. Empty string to not rename. If a list is given, then a NAND-gate structure will be built where the gate nets may be different. Index 0 corresponds to the gate of the source transistor.
s (str) – the source name. Empty string to not rename.
b (str) – the body name. Empty string to not rename.
stack (int) – number of series stack transistors.
mos_type (str) – if non-empty, will change the transistor master to this type.

design_resistor(inst_name: str, unit_params: Mapping[str, Any], nser: int = 1, npar: int = 1, plus: str = '', minus: str = '', mid: str = '', bulk: str = '', connect_mid: bool = True) → None[source]

Design a BAG_prim resistor (with series / parallel support).

This is a convenient method to design a resistor consisting of a series / parallel network of resistor units. For series connections, additional resistors will be created on the right.

Parameters:

inst_name (str) – name of the BAG_prim resistor instance.
unit_params (int) – Parameters of the unit resistor.
nser (int) – number of resistor units in series.
npar (int) – number of resistor units in parallel.
plus (str) – the plus terminal name. Empty string to not rename.
minus (str) – the minus terminal name. Empty string to not rename.
mid (str) – base name of the intermediate nodes for series connection. The intermediate nodes will be named ‘mid_X’, where X is a non-negative integer.
bulk (str) – the bulk terminal name. Empty string to not rename.
connect_mid (bool) – True to connect intermediate nodes (i.e., resistor is constructed as a series of parallel units) False to leave disconnected (i.e., resistor is constructed as series units in parallel)

replace_with_ideal_switch(inst_name: str, rclosed: str = 'rclosed', ropen: str = 'ropen', vclosed: str = 'vclosed', vopen: str = 'vopen')[source]

get_lef_options(options: Dict[str, Any], config: Mapping[str, Any]) → None[source]

Populate the LEF options dictionary.

Parameters:

options (Dict[str, Any]) – the result LEF options dictionary.
config (Mapping[str, Any]) – the LEF configuration dictionary.

get_instance_hierarchy(output_type: pybag.enum.DesignOutput, leaf_cells: Optional[Dict[str, List[str]]] = None, default_view_name: str = '') → Mapping[str, Any][source]

Returns a nested dictionary representing the modeling instance hierarchy.

By default, we try to netlist as deeply as possible. This behavior can be modified by specifying the leaf cells.

Parameters:

output_type (DesignOutput) – the behavioral model output type.
leaf_cells (Optional[Dict[str, List[str]]]) – data structure storing leaf cells.
default_view_name (str) – default model view name.

Returns:

hier – the instance hierarchy dictionary.

Return type:

Mapping[str, Any]

_get_hierarchy_helper(output_type: pybag.enum.DesignOutput, is_leaf_table: Mapping[Tuple[str, str], bool], default_view_name: str) → Optional[Mapping[str, Any]][source]

class bag.design.module.MosModuleBase(yaml_fname: str, database: bag.design.database.ModuleDB, params: bag.util.cache.Param, **kwargs: Any)[source]

Bases: Module

The base design class for the bag primitive transistor.

classmethod is_primitive() → bool[source]

Returns True if this Module represents a BAG primitive.

NOTE: This method is only used by BAG and schematic primitives. This method prevents the module from being copied during design implementation. Custom subclasses should not override this method.

Returns:: is_primitive – True if this Module represents a BAG primitive.
Return type:: bool

classmethod get_params_info() → Mapping[str, str][source]

Returns a dictionary from parameter names to descriptions.

Returns:: param_info – dictionary from parameter names to descriptions.
Return type:: Mapping[str, str]

design(w: int, l: int, nf: int, intent: str) → None[source]

To be overridden by subclasses to design this module.

To design instances of this module, you can call their design() method or any other ways you coded.

To modify schematic structure, call:

get_schematic_parameters() → Mapping[str, str][source]

Returns the schematic parameter dictionary of this instance.

NOTE: This method is only used by BAG primitives, as they are implemented with parameterized cells in the CAD database. Custom subclasses should not override this method.

Returns:: params – the schematic parameter dictionary.
Return type:: Mapping[str, str]

get_cell_name_from_parameters() → str[source]

Returns new cell name based on parameters.

NOTE: This method is only used by BAG primitives. This method enables a BAG primitive to change the cell master based on design parameters (e.g. change transistor instance based on the intent parameter). Custom subclasses should not override this method.

Returns:: cell – the cell name based on parameters.
Return type:: str

should_delete_instance() → bool[source]

Returns True if this instance should be deleted based on its parameters.

This method is mainly used to delete 0 finger or 0 width transistors. However, You can override this method if there exists parameter settings which corresponds to an empty schematic.

Returns:: delete – True if parent should delete this instance.
Return type:: bool

class bag.design.module.DiodeModuleBase(yaml_fname: str, database: bag.design.database.ModuleDB, params: bag.util.cache.Param, **kwargs: Any)[source]

Bases: Module

The base design class for the bag primitive diode.

classmethod is_primitive() → bool[source]

Returns True if this Module represents a BAG primitive.

NOTE: This method is only used by BAG and schematic primitives. This method prevents the module from being copied during design implementation. Custom subclasses should not override this method.

Returns:: is_primitive – True if this Module represents a BAG primitive.
Return type:: bool

classmethod get_params_info() → Mapping[str, str][source]

Returns a dictionary from parameter names to descriptions.

Returns:: param_info – dictionary from parameter names to descriptions.
Return type:: Mapping[str, str]

design(w: int, l: int, intent: str) → None[source]

To be overridden by subclasses to design this module.

To design instances of this module, you can call their design() method or any other ways you coded.

To modify schematic structure, call:

get_schematic_parameters() → Mapping[str, str][source]

Returns the schematic parameter dictionary of this instance.

NOTE: This method is only used by BAG primitives, as they are implemented with parameterized cells in the CAD database. Custom subclasses should not override this method.

Returns:: params – the schematic parameter dictionary.
Return type:: Mapping[str, str]

get_cell_name_from_parameters() → str[source]

Returns new cell name based on parameters.

NOTE: This method is only used by BAG primitives. This method enables a BAG primitive to change the cell master based on design parameters (e.g. change transistor instance based on the intent parameter). Custom subclasses should not override this method.

Returns:: cell – the cell name based on parameters.
Return type:: str

should_delete_instance() → bool[source]

Returns True if this instance should be deleted based on its parameters.

This method is mainly used to delete 0 finger or 0 width transistors. However, You can override this method if there exists parameter settings which corresponds to an empty schematic.

Returns:: delete – True if parent should delete this instance.
Return type:: bool

class bag.design.module.ResPhysicalModuleBase(yaml_fname: str, database: bag.design.database.ModuleDB, params: bag.util.cache.Param, **kwargs: Any)[source]

Bases: Module

The base design class for a real resistor parametrized by width and length.

classmethod is_primitive() → bool[source]

Returns True if this Module represents a BAG primitive.

NOTE: This method is only used by BAG and schematic primitives. This method prevents the module from being copied during design implementation. Custom subclasses should not override this method.

Returns:: is_primitive – True if this Module represents a BAG primitive.
Return type:: bool

classmethod get_params_info() → Mapping[str, str][source]

Returns a dictionary from parameter names to descriptions.

Returns:: param_info – dictionary from parameter names to descriptions.
Return type:: Mapping[str, str]

design(w: int, l: int, intent: str) → None[source]

To be overridden by subclasses to design this module.

To design instances of this module, you can call their design() method or any other ways you coded.

To modify schematic structure, call:

get_schematic_parameters() → Mapping[str, str][source]

Returns the schematic parameter dictionary of this instance.

NOTE: This method is only used by BAG primitives, as they are implemented with parameterized cells in the CAD database. Custom subclasses should not override this method.

Returns:: params – the schematic parameter dictionary.
Return type:: Mapping[str, str]

get_cell_name_from_parameters() → str[source]

Returns new cell name based on parameters.

NOTE: This method is only used by BAG primitives. This method enables a BAG primitive to change the cell master based on design parameters (e.g. change transistor instance based on the intent parameter). Custom subclasses should not override this method.

Returns:: cell – the cell name based on parameters.
Return type:: str

should_delete_instance() → bool[source]

Returns True if this instance should be deleted based on its parameters.

This method is mainly used to delete 0 finger or 0 width transistors. However, You can override this method if there exists parameter settings which corresponds to an empty schematic.

Returns:: delete – True if parent should delete this instance.
Return type:: bool

class bag.design.module.ResMetalModule(yaml_fname: str, database: bag.design.database.ModuleDB, params: bag.util.cache.Param, **kwargs: Any)[source]

Bases: Module

The base design class for a metal resistor.

classmethod is_primitive() → bool[source]

Returns True if this Module represents a BAG primitive.

NOTE: This method is only used by BAG and schematic primitives. This method prevents the module from being copied during design implementation. Custom subclasses should not override this method.

Returns:: is_primitive – True if this Module represents a BAG primitive.
Return type:: bool

classmethod get_params_info() → Mapping[str, str][source]

Returns a dictionary from parameter names to descriptions.

Returns:: param_info – dictionary from parameter names to descriptions.
Return type:: Mapping[str, str]

design(w: int, l: int, layer: int) → None[source]

To be overridden by subclasses to design this module.

To design instances of this module, you can call their design() method or any other ways you coded.

To modify schematic structure, call:

get_schematic_parameters() → Mapping[str, str][source]

Returns the schematic parameter dictionary of this instance.

NOTE: This method is only used by BAG primitives, as they are implemented with parameterized cells in the CAD database. Custom subclasses should not override this method.

Returns:: params – the schematic parameter dictionary.
Return type:: Mapping[str, str]

get_cell_name_from_parameters() → str[source]

Returns new cell name based on parameters.

NOTE: This method is only used by BAG primitives. This method enables a BAG primitive to change the cell master based on design parameters (e.g. change transistor instance based on the intent parameter). Custom subclasses should not override this method.

Returns:: cell – the cell name based on parameters.
Return type:: str

should_delete_instance() → bool[source]

Returns True if this instance should be deleted based on its parameters.

This method is mainly used to delete 0 finger or 0 width transistors. However, You can override this method if there exists parameter settings which corresponds to an empty schematic.

Returns:: delete – True if parent should delete this instance.
Return type:: bool

class bag.design.module.ESDModuleBase(yaml_fname: str, database: bag.design.database.ModuleDB, params: bag.util.cache.Param, **kwargs: Any)[source]

Bases: Module

The base design class for the bag primitive esd (static).

classmethod is_primitive() → bool[source]

Returns True if this Module represents a BAG primitive.

NOTE: This method is only used by BAG and schematic primitives. This method prevents the module from being copied during design implementation. Custom subclasses should not override this method.

Returns:: is_primitive – True if this Module represents a BAG primitive.
Return type:: bool

classmethod get_params_info() → Mapping[str, str][source]

Returns a dictionary from parameter names to descriptions.

Returns:: param_info – dictionary from parameter names to descriptions.
Return type:: Mapping[str, str]

design() → None[source]

To be overridden by subclasses to design this module.

To design instances of this module, you can call their design() method or any other ways you coded.

To modify schematic structure, call:

get_schematic_parameters() → Mapping[str, str][source]

Returns the schematic parameter dictionary of this instance.

NOTE: This method is only used by BAG primitives, as they are implemented with parameterized cells in the CAD database. Custom subclasses should not override this method.

Returns:: params – the schematic parameter dictionary.
Return type:: Mapping[str, str]

class bag.design.module.MIMModuleBase(yaml_fname: str, database: bag.design.database.ModuleDB, params: bag.util.cache.Param, **kwargs: Any)[source]

Bases: Module

The base design class for a mim cap parametrized by width, length, and number of units.

classmethod is_primitive() → bool[source]

Returns True if this Module represents a BAG primitive.

NOTE: This method is only used by BAG and schematic primitives. This method prevents the module from being copied during design implementation. Custom subclasses should not override this method.

Returns:: is_primitive – True if this Module represents a BAG primitive.
Return type:: bool

classmethod get_params_info() → Mapping[str, str][source]

Returns a dictionary from parameter names to descriptions.

Returns:: param_info – dictionary from parameter names to descriptions.
Return type:: Mapping[str, str]

design(unit_width: int, unit_height: int, num_rows: int, num_cols: int, intent: str) → None[source]

To be overridden by subclasses to design this module.

To design instances of this module, you can call their design() method or any other ways you coded.

To modify schematic structure, call: