bag3_digital.design.stdcells.inv.beta
Module Contents
Classes
An inverter design script that sizes the PMOS to have equal pull-up and pull-down strengths. |
Functions
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Returns the parsed parameter file if a Pathlike argument is specified, otherwise passthrough is performed. |
- bag3_digital.design.stdcells.inv.beta.parse_params_file(params: Union[Mapping[str, Any], str, pathlib.Path]) bag.util.immutable.Param [source]
Returns the parsed parameter file if a Pathlike argument is specified, otherwise passthrough is performed.
- class bag3_digital.design.stdcells.inv.beta.InverterBetaDesigner(root_dir: pathlib.Path, sim_db: bag.simulation.cache.SimulationDB, dsn_specs: Mapping[str, Any])[source]
Bases:
bag.simulation.design.DesignerBase
An inverter design script that sizes the PMOS to have equal pull-up and pull-down strengths. The NMOS size is specified directly by the user or the generator specs. The PMOS-to-NMOS ratio (beta) is returned.
- Parameters:
dsn_specs (Mapping[str, Any]) –
The design script specifications. The following entries should be specified:
- gen_specsUnion[Mapping[str, Any], Path, str]
The base/default generator parameters. For each design iteration, new generator parameters will be computed by overriding only the transistor sizing. If a Path or str is specified, the argument will be treated as a path to a specs YAML file.
- meas_paramsMapping[str, Any]
The InvMeas parameters.
- beta_minfloat
The minimum PMOS-to-NMOS ratio. Defaults to 0.25.
- beta_maxfloat
The maximum PMOS-to-NMOS ratio. Defaults to 4.
- seg_nint
Optional. Specify to override the number of NMOS segments in gen_specs.
- property dut_class: Union[Type[bag.layout.template.TemplateBase], Type[bag.design.module.Module]][source]
- classmethod get_dut_gen_specs(is_lay: bool, base_gen_specs: bag.util.immutable.Param, gen_params: Mapping[str, Any]) bag.util.immutable.Param [source]
Compute the new generator parameters by modifying the base parameters.
- Parameters:
- Returns:
output – The new generator specs.
- Return type:
Param
- classmethod get_seg_n(is_lay: bool, gen_specs: bag.util.immutable.Param) int [source]
Return the number of NMOS segments specified in the generator parameters.
- async async_design(beta_min: float = 0.25, beta_max: float = 4, **kwargs: Any) Mapping[str, Any] [source]
A coroutine that designs an inverter with equal pull-up and pull-down. This is done with a binary search on the PMOS sizing.
- Parameters:
- Returns:
output – The design results. Contains the following entries:
- seg_pint
The number of PMOS segments.
- seg_nint
The number of NMOS segments.
- betafloat
The PMOS-to-NMOS ratio.
- delay_error_avgfloat
The delay mismatch.
- Return type:
- static get_seg_p_size_bounds(seg_n: int, beta_min: float, beta_max: float) Tuple[int, int] [source]
Compute the bounds for number of PMOS segments.
- async measure_dut(sim_id: str, dut: bag.simulation.design.DesignInstance) Mapping[str, Any] [source]
A coroutine that measures the delay mismatch between the output rise and fall.
- Parameters:
sim_id (str) – The simulation ID.
dut (DesignInstance) – The DUT to measure.
- Returns:
output – The measurement results. Contains the following entries, in addition to the ones specified in InvMeas:
- delay_errornp.ndarray
The error between pull-up delay and pull-down delay, normalized by the pull-down delay.
- delay_error_avgfloat
The average normalized delay error across all corners and simulation sweeps.
- Return type:
Mapping[str, Any]