bag.simulation.design

Module Contents

Classes

DesignerBase

Base class of all design scripts.
class bag.simulation.design.DesignerBase(root_dir: pathlib.Path, sim_db: bag.simulation.cache.SimulationDB, dsn_specs: Mapping[str, Any])[source]

Bases: bag.util.logging.LoggingBase, abc.ABC

Base class of all design scripts.

Notes

  1. This class hides the SimulationDB object from the user. This is because hierarchical designers share the same SimulationDB, and if you don’t make sure to update the working directory every time you run

property tech_info: bag.layout.tech.TechInfo[source]
property grid: bag.layout.routing.grid.RoutingGrid[source]
property dsn_specs: Dict[str, Any][source]
property extract: bool[source]
property work_dir: pathlib.Path[source]
classmethod get_default_param_values() → Dict[str, Any][source]
classmethod get_dut_class_info(gen_specs: Mapping[str, Any]) → Tuple[bool, Union[Type[bag.layout.template.TemplateBase], Type[bag.design.module.Module]]][source]

Returns information about the DUT generator class.

Parameters:

specs (Param) – The generator specs.

Returns:

  • is_lay (bool) – True if the DUT generator is a layout generator, False if schematic generator.

  • dut_cls (Union[Type[TemplateBase], Type[Module]]) – The DUT generator class.

classmethod design_cell(prj: bag.core.BagProject, specs: Mapping[str, Any], extract: bool = False, force_sim: bool = False, force_extract: bool = False, gen_cell: bool = False, gen_cell_dut: bool = False, gen_cell_tb: bool = False, log_level: pybag.enum.LogLevel = LogLevel.DEBUG) → None[source]
get_design_dir(parent_dir: pathlib.Path) → pathlib.Path[source]
commit() → None[source]

Commit changes to specs dictionary. Perform necessary initialization.

design(**kwargs: Any) → Mapping[str, Any][source]
abstract async async_design(**kwargs: Any) → Mapping[str, Any][source]
run_design() → Mapping[str, Any][source]
set_dsn_specs(specs: Mapping[str, Any]) → None[source]
new_designer(cls: Union[str, Type[DesignerBase]], dsn_specs: Mapping[str, Any]) → DesignerBase[source]
make_tbm(tbm_cls: Union[Type[bag.simulation.core.TestbenchManager], str], tbm_specs: Mapping[str, Any]) → bag.simulation.core.TestbenchManager[source]
make_mm(mm_cls: Union[Type[bag.simulation.measure.MeasurementManager], str], meas_specs: Mapping[str, Any]) → bag.simulation.measure.MeasurementManager[source]
async async_batch_dut(dut_specs: Sequence[Mapping[str, Any]], rcx_params: Optional[Mapping[str, Any]] = None) → Sequence[bag.simulation.cache.DesignInstance][source]
async async_new_dut(impl_cell: str, dut_cls: Union[Type[bag.layout.template.TemplateBase], Type[bag.design.module.Module], str], dut_params: Mapping[str, Any], extract: Optional[bool] = None, name_prefix: str = '', name_suffix: str = '', flat: bool = False, export_lay: bool = False) → bag.simulation.cache.DesignInstance[source]
async async_new_em_dut(impl_cell: str, dut_cls: Union[Type[bag.layout.template.TemplateBase], str], dut_params: Mapping[str, Any], name_prefix: str = '', name_suffix: str = '', flat: bool = False, export_lay: bool = False) → Tuple[bag.simulation.cache.DesignInstance, pathlib.Path, bool][source]
async async_simulate_tbm_obj(sim_id: str, dut: Optional[bag.simulation.cache.DesignInstance], tbm: bag.simulation.core.TestbenchManager, tb_params: Optional[Mapping[str, Any]], tb_name: str = '') → bag.simulation.cache.SimResults[source]
async async_simulate_mm_obj(sim_id: str, dut: Optional[bag.simulation.cache.DesignInstance], mm: bag.simulation.measure.MeasurementManager) → bag.simulation.cache.MeasureResult[source]
async async_gen_nport(dut: bag.simulation.cache.DesignInstance, gds_file: pathlib.Path, gds_cached: bool, em_params: Mapping[str, Any], root_path: pathlib.Path) → pathlib.Path[source]