bag.simulation.cache

This module defines classes and methods to cache previous simulation results.

Module Contents

Classes

DesignInstance

SimResults

MeasureResult

DesignDB

A classes that caches extracted netlists.

SimulationDB

A class that caches netlists, layouts, and simulation results.

Functions

_set_dut(→ Optional[Mapping[str, Any]])

Returns a copy of the testbench parameters dictionary with DUT instantiated.

_set_harnesses(→ Optional[Mapping[str, Any]])

Returns a copy of the testbench parameters dictionary with harness instantiated.
class bag.simulation.cache.DesignInstance[source]
property cache_name: str[source]
property pin_bit_names: Sequence[str][source]
lib_name: str[source]
cell_name: str[source]
sch_master: Optional[bag.design.module.Module][source]
lay_master: Optional[bag.layout.template.TemplateBase][source]
netlist_path: pathlib.Path[source]
cv_info_list: List[pybag.core.PySchCellViewInfo][source]
pin_names: Sequence[str][source]
class bag.simulation.cache.SimResults[source]
dut: Optional[DesignInstance][source]
tbm: bag.simulation.core.TestbenchManager[source]
data: bag.simulation.data.SimData[source]
harnesses: Optional[Sequence[DesignInstance]][source]
class bag.simulation.cache.MeasureResult[source]
dut: Optional[DesignInstance][source]
mm: bag.simulation.measure.MeasurementManager[source]
data: Mapping[str, Any][source]
harnesses: Optional[Sequence[DesignInstance]][source]
class bag.simulation.cache.DesignDB(root_dir: pathlib.Path, log_file: str, db_access: bag.interface.database.DbAccess, sim_netlist_type: pybag.enum.DesignOutput, sch_db: bag.design.database.ModuleDB, lay_db: bag.layout.template.TemplateDB, extract: bool = False, gen_sch_dut: bool = False, gen_sch_tb: bool = False, force_extract: bool = False, log_level: pybag.enum.LogLevel = LogLevel.DEBUG)[source]

Bases: bag.util.logging.LoggingBase

A classes that caches extracted netlists.

property impl_lib: str[source]
property sch_db: bag.design.database.ModuleDB[source]
property gen_sch_dut: bool[source]
property gen_sch_tb: bool[source]
property extract: bool[source]
async async_batch_design(dut_specs: Sequence[Mapping[str, Any]], rcx_params: Optional[Mapping[str, Any]] = None) → Sequence[DesignInstance][source]
async async_new_design(impl_cell: str, dut_cls: Union[Type[bag.layout.template.TemplateBase], Type[bag.design.module.Module], str], dut_params: Mapping[str, Any], extract: Optional[bool] = None, rcx_params: Optional[Mapping[str, Any]] = None, name_prefix: str = '', name_suffix: str = '', flat: bool = False, export_lay: bool = False) → DesignInstance[source]
async async_new_em_design(impl_cell: str, dut_cls: Union[Type[bag.layout.template.TemplateBase], str], dut_params: Mapping[str, Any], name_prefix: str = '', name_suffix: str = '', flat: bool = False, export_lay: bool = False) → Tuple[DesignInstance, pathlib.Path, bool][source]
new_design(impl_cell: str, dut_cls: Union[Type[bag.layout.template.TemplateBase], Type[bag.design.module.Module], str], dut_params: Mapping[str, Any], extract: Optional[bool] = None, rcx_params: Optional[Mapping[str, Any]] = None, export_lay: bool = False) → DesignInstance[source]
async _create_dut(impl_cell: str, dut_cls: Union[Type[bag.layout.template.TemplateBase], Type[bag.design.module.Module], str], dut_params: Mapping[str, Any], extract: Optional[bool] = None, name_prefix: str = '', name_suffix: str = '', flat: bool = False, export_lay: bool = False, em: bool = False) → Tuple[DesignInstance, Optional[pathlib.Path], bool][source]
async gds_check_cache(gds_file: str, cur_dir: pathlib.Path) → bool[source]
async _extract_netlist(dsn_dir: pathlib.Path, impl_cell: str, rcx_params: Mapping[str, Any], static: bool = False, impl_lib: str = '') → None[source]
_generate_cell(impl_cell: str, cdl_netlist: str, gds_file: str) → pathlib.Path[source]
class bag.simulation.cache.SimulationDB(log_file: str, dsn_db: DesignDB, force_sim: bool = False, precision: int = 6, log_level: pybag.enum.LogLevel = LogLevel.DEBUG)[source]

Bases: bag.util.logging.LoggingBase

A class that caches netlists, layouts, and simulation results.

property prj: bag.core.BagProject[source]
property precision: int[source]
property extract: bool[source]
property gen_sch_dut: bool[source]
property gen_sch_tb: bool[source]
make_tbm(tbm_cls: Union[Type[bag.simulation.core.TestbenchManager], str], tbm_specs: Mapping[str, Any], work_dir: Optional[pathlib.Path] = None, tb_name: str = '', logger: Optional[pybag.core.FileLogger] = None) → bag.simulation.core.TestbenchManager[source]
make_mm(mm_cls: Union[Type[bag.simulation.measure.MeasurementManager], str], meas_specs: Mapping[str, Any]) → bag.simulation.measure.MeasurementManager[source]
new_design(impl_cell: str, dut_cls: Union[Type[bag.layout.template.TemplateBase], Type[bag.design.module.Module], str], dut_params: Mapping[str, Any], extract: Optional[bool] = None, rcx_params: Optional[Mapping[str, Any]] = None, export_lay: bool = False) → DesignInstance[source]
simulate_tbm(sim_id: str, sim_dir: pathlib.Path, dut: DesignInstance, tbm_cls: Union[Type[bag.simulation.core.TestbenchManager], str], tb_params: Optional[Mapping[str, Any]], tbm_specs: Mapping[str, Any], tb_name: str = '') → SimResults[source]
simulate_tbm_obj(sim_id: str, sim_dir: pathlib.Path, dut: DesignInstance, tbm: bag.simulation.core.TestbenchManager, tb_params: Optional[Mapping[str, Any]], tb_name: str = '') → SimResults[source]
simulate_mm_obj(sim_id: str, sim_dir: pathlib.Path, dut: Optional[DesignInstance], mm: bag.simulation.measure.MeasurementManager, harnesses: Optional[Sequence[DesignInstance]] = None) → MeasureResult[source]
async async_batch_design(dut_specs: Sequence[Mapping[str, Any]], rcx_params: Optional[Mapping[str, Any]] = None) → Sequence[DesignInstance][source]
async async_new_design(impl_cell: str, dut_cls: Union[Type[bag.layout.template.TemplateBase], Type[bag.design.module.Module], str], dut_params: Mapping[str, Any], extract: Optional[bool] = None, rcx_params: Optional[Mapping[str, Any]] = None, name_prefix: str = '', name_suffix: str = '', flat: bool = False, export_lay: bool = False) → DesignInstance[source]
async async_new_em_design(impl_cell: str, dut_cls: Union[Type[bag.layout.template.TemplateBase], Type[bag.design.module.Module], str], dut_params: Mapping[str, Any], name_prefix: str = '', name_suffix: str = '', flat: bool = False, export_lay: bool = False) → Tuple[DesignInstance, pathlib.Path, bool][source]
async async_simulate_tbm_obj(sim_id: str, sim_dir: pathlib.Path, dut: Optional[DesignInstance], tbm: bag.simulation.core.TestbenchManager, tb_params: Optional[Mapping[str, Any]], tb_name: str = '', harnesses: Optional[Sequence[DesignInstance]] = None) → SimResults[source]
async async_simulate_mm_obj(sim_id: str, sim_dir: pathlib.Path, dut: Optional[DesignInstance], mm: bag.simulation.measure.MeasurementManager, harnesses: Optional[Sequence[DesignInstance]] = None) → MeasureResult[source]
async async_gen_nport(dut: DesignInstance, gds_file: pathlib.Path, gds_cached: bool, em_params: Mapping[str, Any], root_path: pathlib.Path) → pathlib.Path[source]
bag.simulation.cache._set_dut(tb_params: Optional[Mapping[str, Any]], dut_lib: str, dut_cell: str) → Optional[Mapping[str, Any]][source]

Returns a copy of the testbench parameters dictionary with DUT instantiated.

This method updates the testbench parameters dictionary so that the DUT is instantiated statically in the inner-most wrapper.

bag.simulation.cache._set_harnesses(tb_params: Optional[Mapping[str, Any]], harnesses: Optional[Sequence[DesignInstance]] = None) → Optional[Mapping[str, Any]][source]

Returns a copy of the testbench parameters dictionary with harness instantiated.

This method does not support wrappers for harnesses yet. Also harnesses have to be statically instantiated.