bag.core

This is the core bag module.

Module Contents

Classes

BagProject

The main bag controller class.

class bag.core.BagProject

The main bag controller class.

This class mainly stores all the user configurations, and issue high level bag commands.

bag_config

the BAG configuration parameters dictionary.

Type:

Dict[str, Any]

property tech_info: bag.layout.tech.TechInfo

the TechInfo object.

Type:

TechInfo

property grid: bag.layout.routing.grid.RoutingGrid

the global routing grid object.

Type:

RoutingGrid

property default_lib_path: str

property sim_access: bag.simulation.base.SimAccess

property em_sim_access: Optional[bag.simulation.base.EmSimAccess]

close_bag_server() → None

Close the BAG database server.

import_sch_cellview(lib_name: str, cell_name: str, view_name: str = 'schematic') → None

Import the given schematic and symbol template into Python.

This import process is done recursively.

Parameters:

• lib_name (str) – library name.

• cell_name (str) – cell name.

• view_name (str) – view name.

import_design_library(lib_name: str, view_name: str = 'schematic') → None

Import all design templates in the given library from CAD database.

Parameters:

• lib_name (str) – name of the library.

• view_name (str) – the view name to import from the library.

import_gds_file(gds_fname: str, lib_name: str) → None

get_cells_in_library(lib_name: str) → Sequence[str]

Get a list of cells in the given library.

Returns an empty list if the given library does not exist.

Parameters:

lib_name (str) – the library name.

Returns:

cell_list – a list of cells in the library

Return type:

Sequence[str]

make_template_db(log_file: str, impl_lib: str, **kwargs: Any) → bag.layout.template.TemplateDB

Create and return a new TemplateDB instance.

Parameters:

• log_file (str) – the log file path.

• impl_lib (str) – the library name to put generated layouts in.

• **kwargs (Any) – optional TemplateDB parameters.

make_module_db(log_file: str, impl_lib: str, **kwargs: Any) → bag.design.database.ModuleDB

Create and return a new ModuleDB instance.

Parameters:

• log_file (str) – the log file path.

• impl_lib (str) – the library name to put generated layouts in.

• **kwargs (Any) – optional ModuleDB parameters.

make_dsn_db(root_dir: pathlib.Path, log_file: str, impl_lib: str, sch_db: Optional[bag.design.database.ModuleDB] = None, lay_db: Optional[bag.layout.template.TemplateDB] = None, **kwargs: Any) → bag.simulation.cache.DesignDB

make_sim_db(dsn_dir: pathlib.Path, log_file: str, impl_lib: str, dsn_options: Optional[Mapping[str, Any]] = None, **kwargs: Any) → bag.simulation.cache.SimulationDB

get_root_path(root_dir: Union[str, pathlib.Path], use_sim_path: bool = True) → pathlib.Path

static get_dut_class_info(specs: Mapping[str, Any]) → Tuple[bool, Optional[Type[bag.layout.template.TemplateBase]], Optional[Type[bag.design.module.Module]]]

Returns information about the DUT generator class.

Parameters:

specs (Param) – The generator specs.

Returns:

• is_lay (bool) – True if the DUT generator is a layout generator, False if schematic generator.

• lay_cls (Optional[Type[TemplateBase]]) – The DUT layout generator class, if applicable. If schematic generator, then evaluates to None.

• sch_cls (Optional[Type[Module]]) – The DUT schematic generator class. If sch_class is not specified in specs, then evaluates to None.

generate_cell(specs: Dict[str, Any], raw: bool = False, gen_lay: bool = True, gen_sch: bool = True, run_drc: bool = False, run_lvs: bool = False, run_rcx: bool = False, lay_db: Optional[bag.layout.template.TemplateDB] = None, sch_db: Optional[bag.design.database.ModuleDB] = None, gen_lef: bool = False, cv_info_out: Optional[List[pybag.core.PySchCellViewInfo]] = None, sim_netlist: bool = False, flat: bool = False, gen_hier: bool = False, gen_model: bool = False, mismatch: bool = False, gen_shell: bool = False, export_lay: bool = False, gen_netlist: bool = False) → str

Generate layout/schematic of a given cell from specification file.

Parameters:

• specs (Dict[str, Any]) –

  the specification dictionary. Some non-obvious parameters:

  paramsDict[str, Any]

  If layout generator is given, this is the layout parameters. Otherwise this is the schematic parameters.

  netlist_filestr

  If not empty, we will create a netlist file with this name (even if raw = False). if sim_netlist is True, this will be a simulation netlist.

  model_filestr

  the behavioral model filename if gen_model = True.

  gds_filestr

  override the default GDS layout file name. Note that specifying this entry does not mean a GDS file will be created, you must set raw = True or gen_gds = True.

  rcx_paramsOptional[Dict[str, Any]]

  Extra rcx parameters that users can override.

• raw (bool) – True to generate GDS and netlist files instead of OA cellviews.

• gen_lay (bool) – True to generate layout.

• gen_sch (bool) – True to generate schematics.

• run_drc (bool) – True to run DRC.

• run_lvs (bool) – True to run LVS.

• run_rcx (bool) – True to run RCX.

• lay_db (Optional[TemplateDB]) – the layout database.

• sch_db (Optional[ModuleDB]) – the schematic database.

• gen_lef (bool) – True to create LEF file.

• cv_info_out (Optional[List[PySchCellViewInfo]] = None) – If given cellview information objects will be appended to this list.

• sim_netlist (bool) – True to return a simulation netlist.

• flat (bool) – True to generate flat netlist.

• gen_hier (bool) – True to write the system verilog modeling hierarchy in a yaml file.

• gen_model (bool) – True to generate behavioral models

• mismatch (bool) – True to add mismatch voltages

• gen_shell (bool) – True to generate verilog shell file.

• export_lay (bool) – True to export layout file even in non-raw mode.

• gen_netlist (bool) – True to generate netlist even in non-raw mode.

Returns:

rcx_netlist – the extraction netlist. Empty on error or if extraction is not run.

Return type:

str

extract_cell(lib_name: str, cell_name: str, extract_type: Optional[str], extract_corner: Optional[str]) → None

replace_dut_in_wrapper(params: Mapping[str, Any], dut_lib: str, dut_cell: str) → Mapping[str, Any]

simulate_cell(specs: Dict[str, Any], extract: bool = True, gen_tb: bool = True, simulate: bool = True, mismatch: bool = False, raw: bool = True, lay_db: Optional[bag.layout.template.TemplateDB] = None, sch_db: Optional[bag.design.database.ModuleDB] = None) → str

Generate and simulate a single design.

This method only works for simulating a single cell (or a wrapper around a single cell). If you need to simulate multiple designs together, use simulate_config().

Parameters:

• specs (Dict[str, Any]) –

  the specification dictionary. Important entries are:

  use_netliststr

  If specified, use this netlist file as the DUT netlist, and only generate the testbench and simulation netlists. If specified but the netlist does not exist, or the PySchCellViewInfo yaml file does not exist in the same directory, we will still generate the DUT, but the resulting netlist/PySchCellViewInfo object will be saved to this location

• extract (bool) – True to generate extracted netlist.

• gen_tb (bool) –

  True to generate the DUT/testbench/simulation netlists.

  If False, we will simply grab the final simulation netlist and simulate it. This means you can quickly simulate a previously generated netlist with manual modifications.

• simulate (bool) –

  True to run simulation.

  If False, we will only generate the netlists.

• mismatch (bool) – If True mismatch voltage sources are added to the netlist and simulation is done with those in place

• raw (bool) – True to generate GDS and netlist files instead of OA cellviews.

• lay_db (Optional[TemplateDB]) – the layout database.

• sch_db (Optional[ModuleDB]) – the schematic database.

Returns:

sim_result – simulation result file name.

Return type:

str

measure_cell(specs: Mapping[str, Any], extract: bool = False, force_sim: bool = False, force_extract: bool = False, gen_cell: bool = False, gen_cell_dut: bool = False, gen_cell_tb: bool = False, fake: bool = False, log_level: pybag.enum.LogLevel = LogLevel.DEBUG) → None

measure_cell_old(specs: Dict[str, Any], gen_dut: bool = True, load_from_file: bool = False, extract: bool = True, mismatch: bool = False, sch_db: Optional[bag.design.database.ModuleDB] = None, cv_info_list: Optional[List[pybag.core.PySchCellViewInfo]] = None) → Dict[str, Any]

Generate and simulate a single design.

This method only works for simulating a single cell (or a wrapper around a single cell). If you need to simulate multiple designs together, use simulate_config().

Parameters:

• specs (Dict[str, Any]) –

  the specification dictionary. Important entries are:

  use_netliststr

  If specified, use this netlist file as the DUT netlist, and only generate the testbench and simulation netlists.

• gen_dut (bool) – True to generate DUT.

• load_from_file (bool) – True to load from file.

• extract (bool) – True to run extracted simulation.

• mismatch (bool) – If True mismatch voltage sources are added to the netlist and simulation is done with those in place

• sch_db (Optional[ModuleDB]) – the schematic database.

• cv_info_list (Optional[List[PySchCellViewInfo]]) – Optional cellview information objects.

Returns:

meas_result – measurement results dictionary.

Return type:

Dict[str, Any]

run_em_cell(specs: Mapping[str, Any], force_sim: bool = False, log_level: pybag.enum.LogLevel = LogLevel.DEBUG) → None

create_library(lib_name: str, lib_path: str = '') → None

Create a new library if one does not exist yet.

Parameters:

• lib_name (str) – the library name.

• lib_path (str) – directory to create the library in. If Empty, use default location.

instantiate_schematic(lib_name: str, content_list: Sequence[Any], lib_path: str = '') → None

Create the given schematic contents in CAD database.

NOTE: this is BAG’s internal method. To create schematics, call batch_schematic() instead.

Parameters:

• lib_name (str) – name of the new library to put the schematic instances.

• content_list (Sequence[Any]) – list of schematics to create.

• lib_path (str) – the path to create the library in. If empty, use default location.

instantiate_layout_pcell(lib_name: str, cell_name: str, inst_lib: str, inst_cell: str, params: Dict[str, Any], pin_mapping: Optional[Dict[str, str]] = None, view_name: str = 'layout') → None

Create a layout cell with a single pcell instance.

Parameters:

• lib_name (str) – layout library name.

• cell_name (str) – layout cell name.

• inst_lib (str) – pcell library name.

• inst_cell (str) – pcell cell name.

• params (Dict[str, Any]) – the parameter dictionary.

• pin_mapping (Optional[Dict[str, str]]) – the pin renaming dictionary.

• view_name (str) – layout view name, default is “layout”.

instantiate_layout(lib_name: str, content_list: Sequence[Any], lib_path: str = '', view: str = 'layout') → None

Create a batch of layouts.

Parameters:

• lib_name (str) – layout library name.

• content_list (Sequence[Any]) – list of layouts to create

• lib_path (str) – the path to create the library in. If empty, use default location.

• view (str) – layout view name.

release_write_locks(lib_name: str, cell_view_list: Sequence[Tuple[str, str]]) → None

Release write locks from all the given cells.

Parameters:

• lib_name (str) – the library name.

• cell_view_list (Sequence[Tuple[str, str]]) – list of cell/view name tuples.

refresh_cellviews(lib_name: str, cell_view_list: Sequence[Tuple[str, str]]) → None

Refresh the given cellviews in the database.

Parameters:

• lib_name (str) – the library name.

• cell_view_list (Sequence[Tuple[str, str]]) – list of cell/view name tuples.

perform_checks_on_cell(lib_name: str, cell_name: str, view_name: str) → None

Perform checks on the given cell.

Parameters:

• lib_name (str) – the library name.

• cell_name (str) – the cell name.

• view_name (str) – the view name.

run_drc(lib_name: str, cell_name: str, **kwargs: Any) → Tuple[bool, str]

Run DRC on the given cell.

Parameters:

• lib_name (str) – library name.

• cell_name (str) – cell_name

• **kwargs – optional keyword arguments. See DbAccess class for details.

Returns:

• value (bool) – True if DRC succeeds.

• log_fname (str) – name of the DRC log file.

run_lvs(lib_name: str, cell_name: str, **kwargs: Any) → Tuple[bool, str]

Run LVS on the given cell.

Parameters:

• lib_name (str) – library name.

• cell_name (str) – cell_name

• **kwargs – optional keyword arguments. See DbAccess class for details.

Returns:

• value (bool) – True if LVS succeeds

• log_fname (str) – name of the LVS log file.

run_rcx(lib_name: str, cell_name: str, params: Optional[Mapping[str, Any]] = None, **kwargs: Any) → Tuple[str, str]

run RC extraction on the given cell.

Parameters:

• lib_name (str) – library name.

• cell_name (str) – cell name.

• params (Optional[Dict[str, Any]]) – optional RCX parameter values.

• **kwargs – optional keyword arguments. See DbAccess class for details.

Returns:

• netlist (str) – The RCX netlist file name. empty if RCX failed.

• log_fname (str) – RCX log file name.

generate_lef(impl_lib: str, impl_cell: str, verilog_path: pathlib.Path, lef_path: pathlib.Path, run_path: pathlib.Path, options: Dict[str, Any]) → bool

import_layout(in_file: str, lib_name: str, cell_name: str, **kwargs: Any) → str

import layout.

Parameters:

• in_file (str) – input file name.

• lib_name (str) – library name.

• cell_name (str) – cell name.

• **kwargs (Any) – optional keyword arguments. See Checker class for details.

Returns:

log_fname – log file name. Empty if task cancelled.

Return type:

str

export_layout(lib_name: str, cell_name: str, out_file: str, **kwargs: Any) → str

export layout.

Parameters:

• lib_name (str) – library name.

• cell_name (str) – cell name.

• out_file (str) – output file name.

• **kwargs (Any) – optional keyword arguments. See Checker class for details.

Returns:

log_fname – log file name. Empty if task cancelled.

Return type:

str

batch_export_layout(info_list: Sequence[Tuple[Any, Ellipsis]]) → Optional[Sequence[str]]

Export layout of all given cells

Parameters:

info_list –

list of cell information. Each element is a tuple of:

lib_namestr

library name.

cell_namestr

cell name.

out_filestr

layout output file name.

view_namestr

layout view name. Optional.

paramsOptional[Dict[str, Any]]

optional export parameter values.

Returns:

results – If task is cancelled, return None. Otherwise, this is a list of log file names.

Return type:

Optional[Sequence[str]]

async async_run_lvs(lib_name: str, cell_name: str, **kwargs: Any) → Tuple[bool, str]

A coroutine for running LVS.

Parameters:

• lib_name (str) – library name.

• cell_name (str) – cell_name

• **kwargs (Any) – optional keyword arguments. See Checker class for details. LVS parameters should be specified as lvs_params.

Returns:

• value (bool) – True if LVS succeeds

• log_fname (str) – name of the LVS log file.

async async_run_rcx(lib_name: str, cell_name: str, params: Optional[Dict[str, Any]] = None) → Tuple[str, str]

A coroutine for running RCX.

Parameters:

• lib_name (str) – library name.

• cell_name (str) – cell name.

• params (Optional[Dict[str, Any]]) – optional RCX parameter values.

Returns:

• netlist (str) – The RCX netlist file name. empty if RCX failed.

• log_fname (str) – RCX log file name.

create_schematic_from_netlist(netlist: str, lib_name: str, cell_name: str, sch_view: Optional[str] = None, **kwargs: Any) → None

Create a schematic from a netlist.

This is mainly used to create extracted schematic from an extracted netlist.

Parameters:

• netlist (str) – the netlist file name.

• lib_name (str) – library name.

• cell_name (str) – cell_name

• sch_view (Optional[str]) – schematic view name. The default value is implemendation dependent.

• **kwargs (Any) – additional implementation-dependent arguments.

create_verilog_view(verilog_file: str, lib_name: str, cell_name: str, **kwargs: Any) → None

Create a verilog view for mix-signal simulation.

Parameters:

• verilog_file (str) – the verilog file name.

• lib_name (str) – library name.

• cell_name (str) – cell name.

• **kwargs (Any) – additional implementation-dependent arguments.

exclude_model(lib_name: str, cell_name: str) → bool

True to exclude the given schematic generator when generating behavioral models.