xbase.layout.res.base

Module Contents

Classes

ResTermType	Enum where members are also (and must be) ints
ResBasePlaceInfo
ResArrayBase	An abstract template that draws analog resistors array and connections.

class xbase.layout.res.base.ResTermType

Bases: enum.IntEnum

Enum where members are also (and must be) ints

BOT = 0

TOP = 1

BULK = 2

class xbase.layout.res.base.ResBasePlaceInfo(parent_grid: bag.layout.routing.grid.RoutingGrid, wire_specs: Mapping[int, Any], tr_widths: bag.layout.routing.base.WDictType, tr_spaces: bag.layout.routing.base.SpDictType, top_layer: int, nx: int, ny: int, *, conn_layer: Optional[int] = None, res_type: str = 'standard', mos_type: str = '', threshold: str = '', tr_specs: Optional[Sequence[bag.layout.routing.grid.TrackSpec]] = None, half_space: bool = True, ext_mode: xbase.layout.enum.ExtendMode = ExtendMode.AREA, **kwargs: Any)

Bases: xbase.layout.array.base.ArrayPlaceInfo

property res_type: str

property mos_type: xbase.layout.mos.data.MOSType

property threshold: str

property res_config: Mapping[str, Any]

property has_substrate_port: bool

property w_res: int

property l_res: int

compute_hash()

__hash__() → int

Return hash(self).

__eq__(other: Any) → bool

Return self==value.

classmethod get_tech_cls(tech_info: bag.layout.tech.TechInfo, **kwargs: Any) → xbase.layout.res.tech.ResTech

class xbase.layout.res.base.ResArrayBase(temp_db: bag.layout.template.TemplateDB, params: bag.util.immutable.Param, **kwargs: Any)

Bases: xbase.layout.array.base.ArrayBase, abc.ABC

An abstract template that draws analog resistors array and connections.

This template assumes that the resistor array uses 4 routing layers, with directions x/y/x/y. The lower 2 routing layers is used to connect between adjacent resistors, and pin will be drawn on the upper 2 routing layers.

Like for MOSBase, conn_layer should return the top-most layer of the primitive, i.e. the pin layer. We can then connect BBoxs or WireArrays to the pins using the next layer. Unlike BAG2, we assume the conn_layer is BELOW the bottom-most routing layer described above (i.e. below the first horizontal resistor routing layer). This is to allow for more control of the low level wire placement. One effect of this is that resistor primitives can be either WireArrays or BBoxs, so classes using ResArrayBase need to be coded for both. Primitives must be design with connecting to the above horizontal metal in mind.

property has_substrate_port: bool

property sub_type: xbase.layout.mos.data.MOSType

draw_base(obj: Union[ResBasePlaceInfo, Mapping[str, Any]], **kwargs) → ResBasePlaceInfo

get_res_bbox(row_idx: int, col_idx: int) → pybag.core.BBox

Returns the bounding box of the given resistor.

_get_transform(_xidx, _yidx)

get_res_ports(row_idx: int, col_idx: int, top_port_name: str = 'PLUS', bot_port_name: str = 'MINUS') → Union[Tuple[bag.layout.routing.base.WireArray, bag.layout.routing.base.WireArray], Tuple[pybag.core.BBox, pybag.core.BBox]]

Returns the port of the given resistor.

Parameters:

• row_idx (int) – the resistor row index. 0 is the bottom row.

• col_idx (int) – the resistor column index. 0 is the left-most column.

• top_port_name (str) – name of the top port. Defaults to “PLUS”

• bot_port_name (str) – name of the bottom port. Defaults to “MINUS”

Returns:

• bot_warr (WireArray) – the bottom port as WireArray.

• top_warr (WireArray) – the top port as WireArray.

connect_units(warrs: Mapping[int, Mapping[ResTermType, numpy.ndarray]], x0: int, x1: int, y0: int, y1: int) → Tuple[bag.layout.routing.base.WireArray, bag.layout.routing.base.WireArray]

Connect all unit resistors to have parallel connection from x0 to x1 and series from y0 to y1. Returns bottom and top vm_layer WireArrays.

snake_connect_units(warrs: Mapping[int, Mapping[ResTermType, numpy.ndarray]], x0: int, x1: int, y0: int, y1: int) → Tuple[bag.layout.routing.base.WireArray, bag.layout.routing.base.WireArray]

Connect all unit resistors to have snaking series connection from x0 to x1 and from y0 to y1. Returns first and last vm_layer WireArrays.

connect_dummies(warrs: Mapping[int, Mapping[ResTermType, numpy.ndarray]], bulk_warrs: Mapping[int, Union[bag.layout.routing.base.WireArray, Sequence[bag.layout.routing.base.WireArray]]]) → None

Connect all the dummy resistors for the case where dummies are on the periphery.

connect_bulk_xm(warrs: Mapping[int, Sequence[Union[bag.layout.routing.base.WireArray, Sequence[bag.layout.routing.base.WireArray]]]]) → Tuple[bag.layout.routing.base.WireArray, bag.layout.routing.base.WireArray]

Connect all bulk connections to supply on xm_layer

connect_hm_vm(sig_type: str = 'sig') → Tuple[Mapping[int, Mapping[ResTermType, numpy.ndarray]], Mapping[int, Union[bag.layout.routing.base.WireArray, Sequence[bag.layout.routing.base.WireArray]]]]

Connect all resistor ports on hm_layer and vm_layer. BULK ports are shorted. :returns:

hm_layer:

ResTermType.BOT: numpy array of all top hm_layer wires ResTermType.TOP: numpy array of all top vm_layer wires

vm_layer:

ResTermType.BOT: numpy array of all bottom hm_layer wires ResTermType.TOP: numpy array of all bottom vm_layer wires

2. bulk_warrs:

   hm_layer: WireArray with num >= 1 of all hm_layer bulk wires vm_layer: [bottom vm_layer WireArray with num >= 1, top vm_layer WireArray with num >= 1]

Return type:

1. terms

connect_port_hm(port: Union[bag.layout.routing.base.WireArray, pybag.core.BBox, Sequence[bag.layout.routing.base.WireArray, pybag.core.BBox]], adjust: int = 0) → Union[bag.layout.routing.base.WireArray, Sequence[bag.layout.routing.base.WireArray]]

Connects a single or list of resistor port from conn_layer to hm_layer By default, hm wire will be (nearest) centered to the port. If the port needs to be moved, use the adjust option.

Parameters:

port: Union[WireArray, BBox, Sequence[WireArray, BBox]]

Port in question, on conn_layer If a sequence of ports is passed in, function is called on each one

adjust: int

If given, this parameter is passed to get_next_track to get the track id adjust tracks away.

Returns the WireArray or list of WireArrays on hm_layer