bag3_testbenches.schematic.generic_tb

Module Contents

Classes

bag3_testbenches__generic_tb

Module for library bag3_testbenches cell generic_tb.
class bag3_testbenches.schematic.generic_tb.bag3_testbenches__generic_tb(database: bag.design.database.ModuleDB, params: bag.util.immutable.Param, **kwargs: Any)[source]

Bases: bag.design.module.Module

Module for library bag3_testbenches cell generic_tb.

Fill in high level description here.

yaml_file[source]
classmethod get_params_info() → Mapping[str, str][source]

Returns a dictionary from parameter names to descriptions.

Returns:

param_info – dictionary from parameter names to descriptions.

Return type:

Mapping[str, str]

classmethod get_default_param_values() → Mapping[str, Any][source]

Returns a dictionary containing default parameter values.

Override this method to define default parameter values. As good practice, you should avoid defining default values for technology-dependent parameters (such as channel length, transistor width, etc.), but only define default values for technology-independent parameters (such as number of tracks).

Returns:

default_params – dictionary of default parameter values.

Return type:

Mapping[str, Any]

design(dut_lib: str, dut_cell: str, in_file_list: Sequence[Sequence[str]], clk_file_list: Sequence[Sequence[str]], load_list: Optional[Sequence[Sequence[str]]], vbias_list: Optional[Sequence[Sequence[str]]], dut_conns: Mapping[str, str], dut_params: Optional[bag.util.immutable.Param], no_conns: Sequence[str], src_list: Sequence[Mapping[str, Any]], harnesses_cell: Optional[Sequence[Tuple[str, str]]], harnesses_list: Optional[Sequence[Mapping[str, Any]]]) → None[source]

Design the testbench.

The elements of parameter lists are either (pos_term, param) or (pos_term, neg_term, param), where pos_term/neg_term are the positive/negative terminals of the voltage sources or capacitors. The negative terminal defaults to VSS if not specified.

for load_list and vbias_list, if None is given (the default), then the default load/bias voltages will be used (the ones shown in schematic template). If an empty list is given, then they’ll be removed entirely.

Parameters:

  • dut_lib (str) – DUT library name

  • dut_cell (str) – DUT cell name

  • in_file_list (Sequence[Sequence[str]]) – List of PWL input stimuli files

  • clk_file_list (Sequence[Sequence[str]]) – List of PWL clk stimuli files

  • load_list (Optional[Sequence[Sequence[str]]]) – List of ideal capacitor loads

  • vbias_list (Optional[Sequence[Sequence[str]]]) – List of voltage biases

  • dut_conns (Dict[str, str]) – DUT connection dictionary

  • dut_params (Optional[Param]) – Replace the DUT statically if empty, otherwise call design with dut_params.

  • no_conns (List[str]) – Connects the content of this list to noConn.

  • src_list (Sequence[Mapping[str, Any]]) – list of sources and loads.

  • harnesses_cell (Optional[Sequence[Tuple[str, str]]]) – list of available harness lib and cell names

  • harnesses_list (Optional[Sequence[Mapping[str, Any]]]) – list of harnesses used in the TB with harness_idx and conns.

_array_and_set_params(inst_name: str, info_list: Sequence[Sequence[str]], param_name: str, fun: Optional[Callable[[str], str]]) → None[source]