bag3_testbenches.measurement.digital.timing

Module Contents

Classes

CombLogicTimingTB

This class performs timing measurements on combinational logics.

Functions

_write_pwl_file(→ None)

class bag3_testbenches.measurement.digital.timing.CombLogicTimingTB(*args: Any, **kwargs: Any)[source]

Bases: bag.simulation.core.TestbenchManager

This class performs timing measurements on combinational logics.

Assumptions:

  1. tbit is not swept.

  2. power supplies are not swept.

Notes

specification dictionary has the following entries in addition to the default ones:

sim_paramsMapping[str, Any]

Required entries are listed below. In addition, all input output power domain should have their voltage as parameters here.

tbitfloat

the input data waveform bit period.

trffloat

input data rise/fall time, as measured with thres_lo/thres_hi.

Finally, CombLogicTimingTB will define a tsim parameter that is a function of tbit.

thres_lofloat

low threshold for rise/fall time calculation, as fraction of VDD.

thres_hifloat

high threshold for rise/fall time calculation, as fraction of VDD.

stimuli_pwrstr

stimuli voltage power domain parameter name.

save_outputsSequence[str]

list of nets to save in simulation data file.

rtolfloat

relative tolerance for equality checking in timing measurement.

atolfloat

absolute tolerance for equality checking in timing measurement.

tran_optionsMapping[str, Any]

transient simulation options dictionary.

nbit_delayint

Optional. Delay in number of bits. Defaults to 0.

gen_invertbool

Optional. True to generate complementary input waveform on net “inbar”. Defaults to False.

ctrl_paramsMapping[str, Sequence[str]]

Optional. If given, will simulation multiple input pulses, changing control signal values between each pulse. The keys are control signal net names, and values are a list of control signal values for each input pulse. The length of the values list must be the same for all control signals.

clk_paramsDict[str, Any]

Optional. If specified, generate a clock waveform. It has the following entries:

thres_lofloat

low threshold for rise/fall time definition.

thres_hifloat

high threshold for rise/fall time definition.

trfUnion[float, str]

clock rise/fall time, either number in seconds or variable name.

tperUnion[float, str]

clock period, either number in seconds or variable name.

nperint

number of clock periods to generate.

clk_delayUnion[float, str]

the clock delay, either number in seconds or variable name.

clk_pwrstr

the clock power domain parameter name. Defaults to ‘vdd’.

clk_invert: bool

Optional. True to generate inverted clock waveform on net “clkb”. Defaults to False.

tstepOptional[float]

Optional. The strobe period. Defaults to no strobing.

write_numbersbool

Optional. True to write numbers in generated PWL files. Defaults to False.

print_delay_listList[Union[Tuple[str, str], Tuple[str, str, str, str]]]

list of delays to print out in summary report.

print_trf_listList[Union[str, Tuple[str, str]]]

list of rise/fall times to print out in summary report.

classmethod get_schematic_class() → Type[bag.design.module.Module][source]
pre_setup(sch_params: Optional[Mapping[str, Any]]) → Optional[Mapping[str, Any]][source]

Set up PWL waveform files.

get_netlist_info() → bag.simulation.data.SimNetlistInfo[source]

Returns the netlist information object.

Returns:

netlist_info – the simulation netlist information object.

Return type:

SimNetlistInfo

print_results(data: bag.simulation.data.SimData) → None[source]

Override to print results.

calc_output_delay(data: bag.simulation.data.SimData, in_name: str, out_name: str, out_invert: bool, shape: Optional[Tuple[int, Ellipsis]] = None, in_pwr: str = 'vdd', out_pwr: str = 'vdd') → Tuple[numpy.ndarray, numpy.ndarray][source]
calc_output_trf(data: bag.simulation.data.SimData, out_name: str, shape: Optional[Tuple[int, Ellipsis]] = None, out_pwr: str = 'vdd', allow_inf: bool = False) → Tuple[numpy.ndarray, numpy.ndarray][source]
_calc_sim_time_info() → Tuple[int, int][source]
classmethod get_output_delay(data: bag.simulation.data.SimData, specs: Mapping[str, Any], in_name: str, out_name: str, out_invert: bool, shape: Optional[Tuple[int, Ellipsis]] = None, in_pwr: str = 'vdd', out_pwr: str = 'vdd') → Tuple[numpy.ndarray, numpy.ndarray][source]

Compute delay from simulation data.

if the output never resolved correctly, infinity is returned.

Parameters:

  • data (SimData) – Simulation data.

  • specs (Dict[str, Any]) – testbench specs.

  • in_name (str) – input signal name.

  • out_name (str) – output signal name.

  • out_invert (bool) – True if output is inverted from input.

  • shape (Optional[Tuple[int, ...]]) – the delay result output shape.

  • in_pwr (str) – input supply voltage variable name.

  • out_pwr (str) – output supply voltage variable name.

Returns:

  • tdr (np.ndarray) – array of output delay for rising input edge.

  • tdf (np.ndarray) – array of output delay for falling input edge.

classmethod get_output_trf(data: bag.simulation.data.SimData, specs: Mapping[str, Any], out_name: str, shape: Optional[Tuple[int, Ellipsis]] = None, out_pwr: str = 'vdd', allow_inf: bool = False, logger: Optional[pybag.core.FileLogger] = None) → Tuple[numpy.ndarray, numpy.ndarray][source]

Compute output rise/fall time from simulation data.

if output never crosses the high threshold, infinity is returned. If output never crosses the low threshold, nan is returned.

Parameters:

  • data (SimData) – Simulation data.

  • specs (Dict[str, Any]) – testbench specs.

  • out_name (str) – output signal name.

  • shape (Optional[Tuple[int, ...]]) – the delay result output shape.

  • out_pwr (str) – output supply voltage variable name.

  • allow_inf (bool) – Turns off error checking for infinity values Useful for really slow rise/fall times and/or large Cload where the transition is not complete

  • logger (Optional[FileLogger]) – the optional logger object.

Returns:

  • tdr (np.ndarray) – array of output delay for rising input edge.

  • tdf (np.ndarray) – array of output delay for falling input edge.

classmethod compute_output_delay(tvec: numpy.ndarray, in_vec: numpy.ndarray, out_vec: numpy.ndarray, vth_in: float, vth_out: float, out_invert: bool, **kwargs) → Tuple[numpy.ndarray, numpy.ndarray][source]
classmethod compute_output_trf(tvec: numpy.ndarray, yvec: numpy.ndarray, vlo: float, vhi: float, allow_inf: bool = False, logger: Optional[pybag.core.FileLogger] = None, **kwargs: Any) → Tuple[numpy.ndarray, numpy.ndarray][source]
classmethod _trf_helper(t0: numpy.ndarray, t1: numpy.ndarray, allow_inf: bool, tag: str, print_fun: Callable[[str], None]) → numpy.ndarray[source]
classmethod _get_sim_time_info(specs: Mapping[str, Any]) → Tuple[int, int][source]
bag3_testbenches.measurement.digital.timing._write_pwl_file(path: pathlib.Path, data: Union[Sequence[str], Sequence[float]], sim_params: Mapping[str, Union[float, str]], tbit: Union[float, str], trf: Union[float, str], trf_scale: float, nbit_delay: int, write_numbers: bool, tb_scale: float = 1, delay: Union[float, str] = '') → None[source]