bag3_testbenches.measurement.digital.comb

Module Contents

Classes

CombLogicTimingMM

Measures combinational logic delay and rise/fall time of a generic block.

Functions

_get_timing_data(→ Mapping[str, Any])

class bag3_testbenches.measurement.digital.comb.CombLogicTimingMM(*args: Any, **kwargs: Any)

Bases: bag.simulation.measure.MeasurementManager

Measures combinational logic delay and rise/fall time of a generic block.

Assumes that no parameters/corners are swept.

The results follow liberty file convention, i.e. delay_rise is the input-output delay for rising output edge.

Notes

specification dictionary has the following entries:

in_pinUnion[str, Sequence[str]]

input pin(s) to apply PWL waveform.

out_pinUnion[str, Sequence[str]]

output pin(s) to add capacitance loads.

out_invertUnion[bool, Sequence[bool]]

True if waveform at stop is inverted from start. Corresponds to each start/stop pair.

tbm_specsMapping[str, Any]

DigitalTranTB related specifications. The following simulation parameters are required:

t_rst :

reset duration.

t_rst_rf :

reset rise/fall time.

t_bit :

bit value duration.

t_rf :

input rise/fall time

c_load :

load capacitance.

r_src :

source resistance. Only necessary if add_src_res is True.

start_pinUnion[str, Sequence[str]]

Defaults to in_pin. Pins to start measuring delay.

stop_pinUnion[str, Sequence[str]]

Defaults to out_pin. Pins to stop measuring delay.

out_risebool

Defaults to True. True to return delay and rise/fall time for rising output edge.

out_fallbool

Defaults to True. True to return delay and rise/fall time for falling output edge.

wait_cyclesint

Defaults to 0. Number of cycles to wait toggle before finally measuring delay.

add_src_resbool

Defaults to False. True to add source resistance. Will use the variable “r_src”.

wrapper_paramsMapping[str, Any]

Used only if simulated with a DUT wrapper. Contains the following entries:

libstr

wrapper library name.

cellstr

wrapper cell name.

paramsMapping[str, Any]

DUT wrapper schematic parameters.

pinsSequence[str]

wrapper pin list.

load_listOptional[Sequence[Mapping[str, Any]]]

Defaults to None. Extra loads to add to testbench.

fake: bool

Defaults to False. True to generate fake data.

commit() → None

Commit changes to specs dictionary. Perform necessary initialization.

async async_measure_performance(name: str, sim_dir: pathlib.Path, sim_db: bag.simulation.cache.SimulationDB, dut: Optional[bag.simulation.cache.DesignInstance], harnesses: Optional[Sequence[bag.simulation.cache.DesignInstance]] = None) → Mapping[str, Any]

A coroutine that performs measurement.

The measurement is done like a FSM. On each iteration, depending on the current state, it creates a new testbench (or reuse an existing one) and simulate it. It then post-process the simulation data to determine the next FSM state, or if the measurement is done.

Parameters:

• name (str) – name of this measurement.

• sim_dir (Path) – simulation directory.

• sim_db (SimulationDB) – the simulation database object.

• dut (Optional[DesignInstance]) – the DUT to measure.

Returns:

output – the last dictionary returned by process_output().

Return type:

Dict[str, Any]

async _run_sim(name: str, sim_db: bag.simulation.cache.SimulationDB, sim_dir: pathlib.Path, dut: bag.simulation.cache.DesignInstance, tbm: bag3_testbenches.measurement.tran.digital.DigitalTranTB, tb_params: Mapping[str, Any], wait_cycles: int, out_rise: bool, out_fall: bool, is_mc: bool)

bag3_testbenches.measurement.digital.comb._get_timing_data(tbm: bag3_testbenches.measurement.tran.digital.DigitalTranTB, data: bag.simulation.data.SimData, t0: numpy.ndarray, out_pin: str, in_pin: str, out_invert: bool, out_rise: bool, out_fall: bool, is_mc: bool) → Mapping[str, Any]