bag3_digital.design.lvl_shift_ctrl
Module Contents
Classes
- class bag3_digital.design.lvl_shift_ctrl.LvlShiftCtrlDesigner(*args: Any, **kwargs: Any)[source]
Bases:
bag3_digital.design.base.DigitalDesigner- async async_design(cload: float, dmax: float, trf_in: float, tile_specs: Mapping[str, Any], k_ratio: float, tile_name: str, inv_input_cap: float, inv_input_cap_per_fin: float, fanout: float, vin: str, vout: str, w_p: int = 0, w_n: int = 0, ridx_p: int = -1, ridx_n: int = 0, has_rst: bool = False, is_ctrl: bool = False, dual_output: bool = False, exception_on_dmax: bool = True, del_scale: float = 1, **kwargs: Any) Mapping[str, Any][source]
Design a Level Shifter This will try to design a level shifter to meet a maximum nominal delay, given the load cap
- async _find_tgate_and_tint(inv_in_pseg, inv_in_nseg, pseg, nseg, inv_nseg, inv_pseg, out_inv_m, pseg_off, inv_input_cap, cload, k_ratio, pinfo, tbm_specs, is_ctrl, has_rst, dual_output, vin, vout, worst_env) Tuple[dict, dict, float][source]
- async signoff_dut(dut, cload, vin, vout, dmax, trf_in, is_ctrl, has_rst, exception_on_dmax: bool = True) Tuple[float, float, str, float, str][source]
- static _size_input_inv_for_fanout(inv_pseg: int, inv_nseg: int, pseg: int, nseg: int, fanout: float, has_rst: bool) Tuple[int, int][source]
- static _design_lvl_shift_core_size(cload: float, k_ratio: float, inv_input_cap: float, fanout: float, is_ctrl: bool) Tuple[int, int, int][source]
Size the core of the LVL Shifter given K_ratio, the ratio of the NMOS to PMOS
- async _design_lvl_shift_internal_inv(pseg: int, nseg: int, out_inv_m: int, fanout: float, pinfo: Any, tbm_specs: Dict[str, Any], is_ctrl: bool, has_rst: bool, dual_output: bool, vin: str, vout: str) Tuple[int, int][source]
Given the NMOS segments and the PMOS segements ratio for the core, this function designs the internal inverter. For control level shifter, we don’t care about matching rise / fall delay, so we just size for fanout.
- async _design_lvl_shift_inv_pdn(pseg: int, nseg: int, out_inv_m: int, fanout: float, pinfo: Any, tbm_specs: Dict[str, Any], has_rst, dual_output, vin, vout) int[source]
This function figures out the NMOS nseg for the inverter given the target delay TODO: Make this use digitaldB instead
- async _design_lvl_shift_inv_pun(pseg: int, nseg: int, inv_nseg: int, out_inv_m: int, fanout: float, pinfo: Any, tbm_specs: Dict[str, Any], has_rst, dual_output, vin, vout) Tuple[int, int][source]
Given the NMOS pull down size, this function will design the PMOS pull up so that the delay mismatch is minimized. # TODO: Need to double check on how this handles corners
- async _design_output_inverter(inv_in_pseg: int, inv_in_nseg: int, pseg: int, nseg: int, inv_nseg: int, inv_pseg: int, out_inv_m: int, fanout: float, pinfo: Any, tbm_specs: Dict[str, Any], has_rst, vin, vout) int[source]
Given all other sizes and total output inverter segments, this function will optimize the output inverter to minimize rise/fall mismatch.
- static _get_lvl_shift_core_params_dict(pinfo: Any, seg_p: int, seg_n: int, has_rst: bool, is_ctrl: bool = False) Dict[str, Any][source]
Creates a dictionary of parameters for the layout class LevelShifterCore seg_n : nmos Pull down nseg seg_p : pmos Pull up nseg pinfo : pinfo Note: This will let the width be passed through the pinfo, currently no rst
- static _get_lvl_shift_params_dict(pinfo: Any, seg_p: int, seg_n: int, seg_inv_p: int, seg_inv_n: int, seg_in_inv_p: int, seg_in_inv_n: int, out_inv_m: int, has_rst: bool, dual_output: bool, is_ctrl: bool = False, skew_out: bool = False, out_pseg_off: int = 0) Dict[str, Any][source]
Creates a dictionary of parameters for the layout class LevelShifter seg_n : nmos Pull down nseg seg_p : pmos Pull up nseg seg_inv : Inb_buf to In_buf inverter segments seg_in_inv : In to Inb_buf inverter segments pinfo : pinfo # TODO: UPDATE THIS DOCUMENTATION Note: This will let the width be passed through the pinfo, currently no rst