bag3_digital.design.stdcells.se_to_diff

Module Contents

Classes

RCData

DelayData

InvSizeSearch

Helper class that provides a standard way to create an ABC using

SingleToDiffDesigner

Base class of all design scripts.

Functions

_get_delay_err(td1, td2)

_get_dim_str(→ str)

_format_inv_rc(→ Mapping[str, Any])

_format_pg_rc(→ Mapping[str, Any])

class bag3_digital.design.stdcells.se_to_diff.RCData(rc_inv: Mapping[str, Any], rc_pg: Mapping[str, Any])[source]
get_inv_rc(out_rise: Optional[bool], size: float = 1) → Tuple[float, float, float, float][source]
get_pg_rc(out_rise: Optional[bool], size: float = 1) → Tuple[float, float, float][source]
class bag3_digital.design.stdcells.se_to_diff.DelayData[source]
outp: Tuple[float, float][source]
outn: Tuple[float, float][source]
inv2: Tuple[float, float][source]
inv4: Tuple[float, float][source]
get_delay_err(inv2_inv4: bool, out_rise: bool) → float[source]
change_pos(inv2_inv4: bool, out_rise: bool) → bool[source]
get_diff_up(inv2_inv4: bool, out_rise: bool, diff_inc: bool) → Tuple[float, bool][source]
class bag3_digital.design.stdcells.se_to_diff.InvSizeSearch(dsn: SingleToDiffDesigner, dut_params: Dict[str, Any], out_rise: bool, inv2_inv4: bool, diff_inc: bool, size_fun: Callable[[Dict[str, Any], int, int, bool], None], w_list: Sequence[int], err_targ: float, search_step: int = 1)[source]

Bases: bag3_digital.design.base.BinSearchSegWidth

Helper class that provides a standard way to create an ABC using inheritance.

get_bin_search_info(data: DelayData) → Tuple[float, bool][source]
get_error(data: DelayData) → float[source]
set_size(seg: int, w: int) → None[source]
async get_data(seg: int, w: int) → DelayData[source]
class bag3_digital.design.stdcells.se_to_diff.SingleToDiffDesigner(*args: Any, **kwargs: Any)[source]

Bases: bag3_digital.design.base.DigitalDesigner

Base class of all design scripts.

Notes

  1. This class hides the SimulationDB object from the user. This is because hierarchical designers share the same SimulationDB, and if you don’t make sure to update the working directory every time you run

commit() → None[source]

Commit changes to specs dictionary. Perform necessary initialization.

async async_design(**kwargs: Any) → Mapping[str, Any][source]
async get_init_sizing() → Tuple[RCData, Dict[str, Any]][source]
async _get_init_rc() → RCData[source]
async match_delay(se_params: Dict[str, Any], td: DelayData, inv2_inv4: bool) → DelayData[source]
async _match_delay_helper(se_params: Dict[str, Any], td: DelayData, inv2_inv4: bool, out_rise: bool) → DelayData[source]
async sign_off(se_params: Dict[str, Any]) → Mapping[str, Any][source]
_set_inv0_size(se_params: Dict[str, Any], seg: int, w: int, out_rise: bool) → None[source]
_set_inv2_size(se_params: Dict[str, Any], seg: int, w: int, out_rise: bool) → None[source]
_set_inv4_size(se_params: Dict[str, Any], seg: int, w: int, out_rise: bool) → None[source]
async get_cin(dut_params: Mapping[str, Any], rc_data: RCData) → float[source]
async get_delays(se_params: Dict[str, Any]) → DelayData[source]
_get_dim_list(a_min: float, a_max: float, is_pg: bool) → Sequence[Tuple[int, int, int, int]][source]
_get_dimension(area_n: float, is_pg: bool) → Tuple[int, int, int, int][source]
_get_seg_w(area: float) → Tuple[int, int][source]
bag3_digital.design.stdcells.se_to_diff._get_delay_err(td1: float, td2: float)[source]
bag3_digital.design.stdcells.se_to_diff._get_dim_str(params: Mapping[str, int]) → str[source]
bag3_digital.design.stdcells.se_to_diff._format_inv_rc(rc_dict: Mapping[str, Any], w_norm: int) → Mapping[str, Any][source]
bag3_digital.design.stdcells.se_to_diff._format_pg_rc(rc_dict: Mapping[str, Any], w_norm: int) → Mapping[str, Any][source]