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"""This module defines programmable series / parallel combination of resistor units for characterization."""
from typing import Mapping, Any, Optional, Type, cast
from bag.util.immutable import Param
from bag.design.module import Module
from bag.layout.template import TemplateDB
from bag.layout.routing.base import TrackID
from pybag.enum import RoundMode
from .base import ResBasePlaceInfo, ResArrayBase
from ...schematic.res_char import xbase__res_char
[docs]class ResChar(ResArrayBase):
"""Programmable series / parallel combination of unit resistors"""
def __init__(self, temp_db: TemplateDB, params: Param, **kwargs: Any) -> None:
ResArrayBase.__init__(self, temp_db, params, **kwargs)
@classmethod
[docs] def get_schematic_class(cls) -> Optional[Type[Module]]:
return xbase__res_char
@classmethod
[docs] def get_params_info(cls) -> Mapping[str, str]:
return dict(
pinfo='The ResBasePlaceInfo object.',
)
[docs] def draw_layout(self) -> None:
pinfo = cast(ResBasePlaceInfo, ResBasePlaceInfo.make_place_info(self.grid, self.params['pinfo']))
self.draw_base(pinfo)
# Get hm_layer and vm_layer WireArrays
warrs, bulk_warrs = self.connect_hm_vm()
# Supply connections on xm_layer
self.connect_bulk_xm(bulk_warrs)
# --- Routing of unit resistors --- #
minus, plus = self.connect_units(warrs, 0, pinfo.nx, 0, pinfo.ny)
hm_layer = self.conn_layer + 1
vm_layer = hm_layer + 1
xm_layer = vm_layer + 1
w_xm_sig = self.tr_manager.get_width(xm_layer, 'sig')
for pin_name, warr in [('minus', minus), ('plus', plus)]:
xm_idx = self.grid.coord_to_track(xm_layer, warr.middle, RoundMode.NEAREST)
xm_tid = TrackID(xm_layer, xm_idx, w_xm_sig)
self.add_pin(pin_name, self.connect_to_tracks(warr, xm_tid))
self.sch_params = dict(
unit_params=dict(
w=pinfo.w_res,
l=pinfo.l_res,
intent=pinfo.res_type,
),
nser=pinfo.ny,
npar=pinfo.nx,
sub_type=pinfo.res_config['sub_type_default'],
)