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# Copyright 2019 Blue Cheetah Analog Design Inc.
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from typing import Dict, Any
import pkg_resources
from pathlib import Path
from bag.design.module import Module
from bag.design.database import ModuleDB
from bag.util.immutable import Param
# noinspection PyPep8Naming
[docs]class bag3_digital__latch(Module):
"""Module for library bag3_digital cell latch.
Fill in high level description here.
"""
[docs] yaml_file = pkg_resources.resource_filename(__name__,
str(Path('netlist_info',
'latch.yaml')))
def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
Module.__init__(self, self.yaml_file, database, params, **kwargs)
@classmethod
[docs] def get_params_info(cls) -> Dict[str, str]:
return dict(
lch='channel length.',
w_p='PMOS width.',
w_n='NMOS width.',
th_p='PMOS threshold.',
th_n='NMOS threshold.',
seg_dict='Segments dictionary.',
)
[docs] def design(self, lch: int, w_p: int, w_n: int, th_p: str, th_n: str, seg_dict: Dict[str, int]
) -> None:
self.instances['XTBUF'].design(lch=lch, w_p=w_p, w_n=w_n, th_p=th_p, th_n=th_n,
seg=seg_dict['tin'])
self.instances['XTFB'].design(lch=lch, w_p=w_p, w_n=w_n, th_p=th_p, th_n=th_n,
seg=seg_dict['tfb'])
self.instances['XBUF'].design(lch=lch, w_p=w_p, w_n=w_n, th_p=th_p, th_n=th_n,
seg=seg_dict['buf'])
self.instances['XCM'].design(nin=2)