# BSD 3-Clause License
#
# Copyright (c) 2018, Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# * Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
#
# * Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# * Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# -*- coding: utf-8 -*-
from typing import Mapping, Any
import pkg_resources
from pathlib import Path
from bag.design.module import Module
from bag.design.database import ModuleDB
from bag.util.immutable import Param
# noinspection PyPep8Naming
[docs]class bag3_analog__res_dummy(Module):
"""Dummy resistor, used in high pass array
"""
[docs] yaml_file = pkg_resources.resource_filename(__name__,
str(Path('netlist_info',
'res_dummy.yaml')))
def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
Module.__init__(self, self.yaml_file, database, params, **kwargs)
@classmethod
[docs] def get_params_info(cls) -> Mapping[str, str]:
return dict(
l='unit resistor length, in meters.',
w='unit resistor width, in meters.',
intent='resistor type.',
ndum='number of dummy resistors.',
sub_name='substrate name. Empty string to disable.',
)
@classmethod
[docs] def get_default_param_values(cls) -> Mapping[str, Any]:
return dict(
sub_name='VSS',
)
[docs] def design(self, l: int, w: int, intent: str, ndum: int, sub_name: str):
# handle substrate pin
if not sub_name:
# delete substrate pin
self.remove_pin('BULK')
else:
self.rename_pin('BULK', sub_name)
# design dummy
if ndum == 0:
self.delete_instance('XDUM')
else:
unit_params = dict(w=w, l=l, intent=intent)
self.design_resistor('XDUM', unit_params, 1, ndum, sub_name, sub_name, bulk=sub_name)